74.10 Operation and Power Consumption in Low-Power Modes
The SAMA7G5 features six low-power modes summarized in the following table. A detailed description of each mode is provided in the following sections.
| Low-Power Mode | |||||||
|---|---|---|---|---|---|---|---|
| Backup Mode | BSR | ULP2 | ULP1 | ULP0 | Idle | ||
| VBAT Power | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | |
| VDDCPU Power | ✗ | ✗ | ✗ | ✓ | ✓ | ✓ | |
| VDDCORE Power | ✗ | ✗ | ✓ | ✓ | ✓ | ✓ | |
| SDRAM or DDR Power | ✗ | ✓ | ✓ | ✓ | ✓ | ✓ | |
| DDR Self-refresh | ✗ | ✓ | ✓ | ✓ | ✓ | ✗ | |
| Main Crystal Oscillator | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | |
| Main RC Oscillator | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | |
| Main Clock (MAINCK) | Source (MOSCSEL) | – | – | Main RC osc. | Main RC osc. | User-defined | User-defined |
| Status | – | – | ✗ | ✗ | User-defined | ✓ | |
| Main System Bus Clock (MCK1) | Source (CSS) | – | – | MAINCK | MAINCK | User-defined (MD_SLCK, MAINCK etc.) | User-defined (PLLs, etc.) |
| Status | – | – | ✗ | ✗ | ✓ | ✓ | |
| CPU Clock (CPU_CLK) | – | – | ✗ | ✗ | ✓ | ✓ | |
| Cortex-A7 State | Not powered | Not powered | Not powered | Clocks stopped | WFI | WFI | |
| Mode Entry |
Use SHDWC to shut down all power supplies except VBAT. |
Context saved in SDRAM. SDRAM in Self-refresh. Use SHDWC to shut down all power supplies except VDDIODDR and VBAT. |
Set AUTOLPM bit. Context saved in SDRAM. SDRAM in Self-refresh. ULP2 bit. |
Context saved in SDRAM. SDRAM in Self-refresh. ULP1 bit |
Context saved in SDRAM. SDRAM in Self-refresh. WFI. |
WFI |
|
| Wake-up | Sources |
RTC/RTT alarm. WKUP0, SECUMOD events through WKUP1 and PIOBU[3:0]. |
RTC/RTT alarm. WKUP0, SECUMOD events through WKUP1 and PIOBU[3:0]. |
Any PIO line. RTC/RTT alarm. USB resume. |
Any PIO line. RTC/RTT alarm. USB resume. |
Any unmasked interrupt |
Any unmasked interrupt |
| Event Sampling Clock | MD_SLCK | MD_SLCK | Asynchronous | Asynchronous | User-defined (MD_SLCK, MAINCK division, etc.) | User-defined (MCKx, periph_clk, etc.) | |
| Main System Bus Clock (MCK1) at Wake-up | MAINCK (defaults to Main RC osc.) | MAINCK (defaults to Main RC osc.) | MAINCK (configured to Main RC osc.) | MAINCK (configured to Main RC osc.) | MD_SLCK | User-defined | |
| Wake-up Time (time to fetch first instruction) |
- | - | See Table 74-79 | ||||
- ✓ / ✗ means either powered/un-powered for a power source, on/off for an oscillator, active/inactive for a clock signal, or enter/exit Self-Refresh mode for the external SDRAM.