18.3.2.2 SDRAM Initialization

Important: The DDR3PHY registers, SDRAM mode registers, and equivalent register fields inside the memory controller (UDDRC) must be uniformly programmed. Mismatches between the register fields can cause transaction failures. Verify all register fields are consistently programmed before starting any SDRAM transactions.

Prior to normal operation, DDR SDRAMs must be initialized. The DDR3PHY has a built-in SDRAM initialization routine that may be triggered by software or memory controller by writing to DDR3PHY_PIR. The initialization routine built into the DDR3PHY is generic and does not require any knowledge of the type or configuration of external SDRAMs to be properly executed. The routine is designed with the relevant JEDEC specifications for the fastest and slowest SDRAMs supported by the DDR3PHY to result in a universal initialization sequence. This generic sequence is applied to DDR3, DDR2, LPDDR3 and LPDDR2 SDRAMs during the SDRAM initialization sequence. Refer to "SDRAM Initialization Sequence" in the section "Universal DDR Memory Controller (UDDRC)".