8.2 System Interconnect Overview

The following table shows allowed paths (X).

Table 8-6. System Interconnections
UDDRC_P0 – MCK4 UDDRC_P1 – MCK1 UDDRC_P2 – MCK1 UDDRC_P3 – MCK3 UDDRC_P4 – MCK1 OTPC – MCK0 CPKCC RAM/ROM – MCK0 APB0 – MCK0 APB1 – MCK1 APB2 – MCK1 APB3 – MCK1 APB4 – MXK1 APB5 – MCK1 APB6 – MCK1 APB7 – MCK1 USB_RAM – MCK1 SRAM_P0 – MCK1 SRAM_P1 – MCK1 TZAESB – MCK1 SMC – MKC1 QSPI0 – MCK1 QSPI1 – MCK1 NFC_RAM – MCK1 NFC_CMD – MCK1 UHPHS_OHCI/EHCI – MCK1 APB_DBG/APB_DBG_S – MCK1 NICGPV – MCK1 CSI2DC_META – MCK1 ROM/ ECC_ROM – MCK0
TrustZone Management Location(1) TZC TZC TZC TZC TZC AS(2) AS (2) AS(2) TZPM TZPM TZPM TZPM TZPM TZPM TZPM MATRIX MATRIX MATRIX TZAESBAS -CTZPM MATRIX MATRIX MATRIX MATRIX MATRIX MATRIX MATRIX AS(2) MCK1 MCK0
CA7 – MCK4 Supervi-sor mode or CP15 X X X X X X X X X X X X X X X X X X X X X X X
XDMAC0–MCK1 XDMAC0 X X X X X X X X X X X X
XDMAC1–MCK1 XDMAC1 X X X X X X X X X X X X
GMAC0–MCK1 TZPM X X X X X
GMAC1–MCK1 TZPM X X X X X
SDMMC0–MCK1 TZPM X X X X X
SDMMC1–MCK1 TZPM X X X X X
SDMMC2–MCK1 TZPM X X X X X
XDMAC2–MCK1 XDMAC2 X X X X X X X X
MCAN0 – MCK1 TZPM X
MCAN1–MCK1 TZPM X
MCAN2–MCK1 TZPM X
MCAN3–MCK1 TZPM X
MCAN4–MCK1 TZPM X
MCAN5–MCK1 TZPM X
ICM–MCK1 TZPM X X X X X
UDPHS0_DMA–MCK1 TZPM X X
UDPHS1_DMA–MCK1 TZPM X X
OHCI_DMA – MCK1 TZPM X X
EHCI_DMA–MCK1 TZPM X X
TZAESB–MCK1 TZAESBASC X X X X X
ISC–MCK3 TZPM X
Note:
  1. Refer to the following sections for details on each configuration method.
  2. “AS” stands for Always Secure; this configuration cannot be changed.