8.1 System Bus and Interconnect

The device on-chip interconnect is architectured around the following components:

5x AXI matrixes based on the Arm NIC-400 module
1x AHB matrix
8x APB buses
1x Universal DDR Memory Controller (UDDRC)

The following features are supported by the interconnect backbone:

Quality of Service (QoS) to ensure priorities and limits for all AXI and AHB transactions
Performance monitoring to track AXI bus activity

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