55.5.12 SHA Write Protection Status Register
Name: | SHA_WPSR |
Offset: | 0xE8 |
Reset: | 0x00000000 |
Property: | Read-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
ECLASS | SWETYP[3:0] | ||||||||
Access | R | R | R | R | R | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
Access | |||||||||
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
WPVSRC[7:0] | |||||||||
Access | R | R | R | R | R | R | R | R | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
SWE | SEQE | CGD | WPVS | ||||||
Access | R | R | R | R | |||||
Reset | 0 | 0 | 0 | 0 |
Bit 31 – ECLASS Software Error Class (cleared on read)
0 (WARNING): An abnormal access that does not affect system functionality
1 (ERROR): An access is performed into key, input data, control registers while the SHA is performing an encryption/decryption or a start is request by software or DMA while the key is not fully configured.
Bits 27:24 – SWETYP[3:0] Software Error Type (cleared on read)
Value | Name | Description |
---|---|---|
0 | READ_WO | A write-only register has been read (Warning). |
1 | WRITE_RO | SHA is enabled and a write access has been performed on a read-only register (Warning). |
2 | UNDEF_RW | Access to an undefined address (Warning). |
3 | CTRL_START | SHA is locked and a start command with SHA_CR.START has been performed. |
4 | AUTO_START | SHA is locked and a tentative automatic start has been performed by writing input data registers (SHA_MR.SMOD>0). |
5 | BAD_START | SHA is not locked and a start command with SHA_CR.START has been performed whereas Start mode is automatic (SHA_MR.SMOD>0) |
Bits 15:8 – WPVSRC[7:0] Write Protection Violation Source
When WPVS=1, WPVSRC indicates the register address offset at which a write access has been attempted.
When WPVS=0 and SWE=1, WPVSRC reports the address of the incorrect software access. As soon as WPVS=1, WPVSRC returns the address of the write-protected violation.
Bit 3 – SWE Software Control Error (cleared on read)
Value | Description |
---|---|
0 | No software error has occurred since the last read of SHA_WPSR. |
1 | A software error has occurred since the last read of SHA_WPSR. The field SWETYP details the type of software error; the associated incorrect software access is reported in the field WPVSRC (if WPVS=0). |
Bit 2 – SEQE Internal Sequencer Error (cleared on read)
Value | Description |
---|---|
0 | No peripheral internal sequencer error has occurred since the last read of SHA_WPSR. |
1 | A peripheral internal sequencer error has occurred since the last read of SHA_WPSR. This flag can only be set under abnormal operating conditions. |
Bit 1 – CGD Clock Glitch Detected (cleared on read)
Value | Description |
---|---|
0 | The clock monitoring circuitry has not been corrupted since the last read of SHA_WPSR. Under normal operating conditions, this bit is always cleared. |
1 | The clock monitoring circuitry has been corrupted since the last read of SHA_WPSR. This flag can only be set in case of an abnormal clock signal waveform (glitch). |
Bit 0 – WPVS Write Protection Violation Status (cleared on read)
Value | Description |
---|---|
0 | No write protect violation has occurred since the last read of SHA_WPSR. |
1 | A write protect violation has occurred since the last read of SHA_WPSR. The address offset of the violated register is reported into field WPVSRC. |