57.6.2 TRNG Mode Register

This register can only be written if the WPEN bit is cleared in the TRNG Write Protection Mode Register.

Name: TRNG_MR
Offset: 0x04
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
        HALFR 
Access R/W 
Reset 0 

Bit 0 – HALFR Half Rate Enable

ValueNameDescription
0 DISABLED Maximum stream rate provided (1 sample every 84 MCK clock cycles).
1 ENABLED Half maximum stream rate provided if the peripheral clock frequency is above 100 MHz (1 sample every 168 MCK clock cycles).