Jump to main content
Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security
Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security
Product Pages
SAMA7G54
  1. Home
  2. 63 Flexible Serial Communication Controller (FLEXCOM)
  3. 63.9 TWI Functional Description
  4. 63.9.6 TWI FIFOs
  5. 63.9.6.4 Sending/Receiving with FIFO Enabled in Client Mode
  • Introduction
  • Features
  • Reference Document
  • 1 Configuration Summary
  • 2 Block Diagram
  • 3 Signal Description
  • 4 Microchip Recommended Power Management Solutions
  • 5 Safety and Security Features
  • 6 Event System
  • 7 Package and Pinout
  • 8 System Interconnect and Security (SIS)
  • 9 Cortex-A7 Processor (Arm)
  • 10 External Interrupt Controller (EIC)
  • 11 Debug and Test
  • 12 NIC-400 Global Programmer’s View (NICGPV)
  • 13 Bus Matrix (MATRIX)
  • 14 DMA Controller (XDMAC)
  • 15 MEMORIES
  • 16 Static Memory Controller (SMC)
  • 17 Universal DDR Memory Controller (UDDRC)
  • 18 DDR/LPDDR Physical Interface (DDR3PHY)
  • 19 Boot Strategies
  • 20 SYSTEM CONTROLLER SUBSYSTEM
  • 21 System Controller Write Protection (SYSCWP)
  • 22 General Purpose Backup Registers (GPBR)
  • 23 Dual Watchdog Timer (DWDT)
  • 24 Reset Controller (RSTC)
  • 25 Real-Time Timer (RTT)
  • 26 Real-Time Clock (RTC)
  • 27 Shutdown Controller (SHDWC)
  • 28 64-bit Periodic Interval Timer (PIT64B)
  • 29 Chip Identifier (CHIPID)
  • 30 OTP Memory Controller (OTPC)
  • 31 Special Function Registers (SFR)
  • 32 Special Function Registers Backup (SFRBU)
  • 33 Slow Clock Controller (SCKC)
  • 34 Clock Generator
  • 35 Power Management Controller (PMC)
  • 36 Parallel Input/Output Controller (PIO)
  • 37 ANALOG SUBSYSTEM
  • 38 Analog-to-Digital Converter (ADC) Controller
  • 39 Analog Comparator Controller (ACC)
  • 40 IMAGE SUBSYSTEM
  • 41 Camera Serial Interface (CSI)
  • 42 CSI-2 Demultiplexer Controller (CSI2DC)
  • 43 Image Sensor Controller (ISC)
  • 44 AUDIO SUBSYSTEM
  • 45 Inter-IC Sound Multi-Channel Controller (I2SMCC)
  • 46 Synchronous Serial Controller (SSC)
  • 47 Sony/Philips Digital Interface Receiver (SPDIFRX)
  • 48 Sony/Philips Digital Interface Transmitter (SPDIFTX)
  • 49 Pulse Density Microphone Controller (PDMC)
  • 50 Asynchronous Sample Rate Converter (ASRC)
  • 51 CRYPTOGRAPHY SUBSYSTEM
  • 52 TrustZone Advanced Encryption Standard Bridge (TZAESB)
  • 53 TrustZone AES Bridge Address Space Controller (TZAESBASC)
  • 54 Advanced Encryption Standard (AES)
  • 55 Secure Hash Algorithm (SHA)
  • 56 Triple Data Encryption Standard (TDES)
  • 57 Random Number Generator (TRNG)
  • 58 Integrity Check Monitor (ICM)
  • 59 Classical Public Key Cryptography Controller (CPKCC)
  • 60 Security Module (SECUMOD)
  • 61 CONNECTIVITY SUBSYSTEM
  • 62 Gigabit Ethernet MAC (GMAC)
  • 63 Flexible Serial Communication Controller (FLEXCOM)
    • 63.1 Description
    • 63.2 Embedded Characteristics
    • 63.3 Block Diagram
    • 63.4 I/O Lines Description
    • 63.5 Product Dependencies
    • 63.6 Register Accesses
    • 63.7 USART Functional Description
    • 63.8 SPI Functional Description
    • 63.9 TWI Functional Description
      • 63.9.1 Transfer Format
      • 63.9.2 Modes of Operation
      • 63.9.3 Host Mode
      • 63.9.4 Multi-Host Mode
      • 63.9.5 Client Mode
      • 63.9.6 TWI FIFOs
        • 63.9.6.1 Overview
        • 63.9.6.2 Sending Data with FIFO Enabled
        • 63.9.6.3 Receiving Data with FIFO Enabled
        • 63.9.6.4 Sending/Receiving with FIFO Enabled in Client Mode
        • 63.9.6.5 Clearing/Flushing FIFOs
        • 63.9.6.6 TXRDY and RXRDY Behavior
        • 63.9.6.7 TWI Single Data Access
        • 63.9.6.8 TWI Multiple Data Access
        • 63.9.6.9 Transmit FIFO Lock
        • 63.9.6.10 FIFO Pointer Error
        • 63.9.6.11 FIFO Thresholds
        • 63.9.6.12 FIFO Flags
      • 63.9.7 TWI Comparison Function on Received Character
      • 63.9.8 Sniffer Mode
      • 63.9.9 TWI Register Write Protection
    • 63.10 Register Summary
  • 64 Quad Serial Peripheral Interface (QSPI)
  • 65 Secure Digital MultiMedia Card Controller (SDMMC)
  • 66 Controller Area Network (MCAN)
  • 67 Timer Counter (TC)
  • 68 Pulse Width Modulation Controller (PWM)
  • 69 USB SUBSYSTEM
  • 70 USB Type-C™ Port Controller (TCPC)
  • 71 USB 2.0 PHY
  • 72 USB Device High Speed Port (UDPHS)
  • 73 USB Host High Speed Port (UHPHS)
  • 74 Electrical Characteristics
  • 75 Mechanical Characteristics
  • 76 Marking
  • 77 Ordering Information
  • 78 Glossary
  • 79 Revision History
  • Microchip Information

63.9.6.4 Sending/Receiving with FIFO Enabled in Client Mode

See Sending Data with FIFO Enabled and Receiving Data with FIFO Enabled for details.

Figure 63-132. Sending/Receiving Data with FIFO Enabled in Client Mode

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

Microchip Facebook
Microchip LinkedIn
Microchip Twitter
Microchip YouTube
Microchip Instagram
Microchip Weibo
Microchip Blog
Contact |
Legal |
Privacy Policy |
Cookies |
Careers

Stay on the leading edge with our blog

MicroSolutions

© Copyright 1998-2022 Microchip Technology Inc. All rights reserved.