17.4.2 Implementation Example
| DDR Controller Signal | LPDDR2 Signal |
|---|---|
| DDR_A0 | CA0 |
| DDR_A1 | CA1 |
| DDR_A2 | CA2 |
| DDR_A3 | CA3 |
| DDR_A4 | CA4 |
| DDR_A5 | CA5 |
| DDR_A6 | CA6 |
| DDR_A7 | CA7 |
| DDR_A8 | CA8 |
| DDR_A9 | CA9 |
| Higher addresses | Higher CAs |
| DDR Controller Signal | LPDDR2 Signal |
|---|---|
| DDR_A0 | CA0 |
| DDR_A1 | CA1 |
| DDR_A2 | CA2 |
| DDR_A3 | CA3 |
| DDR_A4 | CA4 |
| DDR_A5 | CA5 |
| DDR_A6 | CA6 |
| DDR_A7 | CA7 |
| DDR_A8 | CA8 |
| DDR_A9 | CA9 |
| Higher addresses | Higher CAs |
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