19.1.3 Chip Setup

When the chip is powered on, the processor clock (CPU_CLK) and the main system bus clock (MCK0) source is the main clock (MAINCK), which is fed by the main RC oscillator.

The ROM code performs a low-level initialization that follows the steps described below:
  1. SYSPLL is initialized.
  2. MCK1 is initialized and sourced by SYSPLL.
  3. MCK4 is initialized and sourced by SYSPLL.
  4. CPUPLL is initialized.
  5. When the CPUPLL is stabilized, the main system bus clock (MCK0) source is switched from the main clock (MAINCK) to the CPUPLL clock. The CPU_CLK frequency is the same as the CPUPLL clock, whereas the MCK0 frequency is the quarter of the CPUPLL clock.

For clock frequencies, see the table Clock Frequencies During External Memory Boot Sequence.

Note: No external crystal or clock is needed during the external boot memories sequence. An external clock source is checked before the launch of the monitor to get a more accurate clock signal for USB.