2.2.1 Pinout Details

The ATWILC3000A is offered in an exposed pad 48-pin QFN package. This package contains an exposed paddle that must be connected to the system board ground. The following figure shows the QFN package pin assignment. The color shading indicates the pin type as follows:

Green – Power
Red – Analog
Blue – Digital I/O
Yellow – Digital input
Grey – Not connected or reserved

The following table provides the ATWILC3000A pin description.

Table 2-1. ATWILC3000A Pin Description
Pin #	Pin Name	Pin Type	Description
1	VDDRF_RX	Power	Tuner RF RX supply
2	VDDAMS	Power	Tuner BB supply
3	VDDRF_TX	Power	Tuner RF TX supply
4	VBAT_PA	Power	Power supply pin for DC/DC converter and PA
5	RFIOP	Analog	Wi-Fi^®/Bluetooth^® positive RF differential I/O
6	RFION	Analog	Wi-Fi/Bluetooth negative RF differential I/O
7	NC1	—	No connection
8	NC2	—	No connection
9	NC3	—	No connection
10	NC4	—	No connection
11	TEST_MODE	Digital Input	Test mode – the user must connect this pin to a ground
12	SDIO_SPI_CFG	Digital Input	Connect to VDDIO through a 1 MΩ resistor to enable SPI interface Connect to GND to enable SDIO interface
13	RESETN	Digital Input	Active-low hard Reset When this pin is asserted low, the module is placed in the Reset state When this pin is asserted high, the module is taken out of Reset and functions normally Connect to a host output that defaults low on power-up; if the host output is tri-stated, add a 1 MΩ pull-down resistor to ensure a low level at power-up
14	BT_TXD	Digital I/O, Programmable Pull-up	Bluetooth UART transmit data output Connect to UART_RXD of host
15	BT_RXD	Digital I/O, Programmable Pull-up	Bluetooth UART receive data input Connect to UART_TXD of host
16	BT_RTS/I2C_SDA_S	Digital I/O, Programmable Pull-up	I²C Client data Used only for debug development purposes Adding a test point for this pin is recommended. I²C will be the default configuration. If flow control is enabled, this pin will be configured as UART RTS.
17	BT_CTS/I2C_SCL_S	Digital I/O, Programmable Pull-up	I²C Client clock Used only for debug development purposes Adding a test point for this pin is recommended. I²C will be the default configuration. If flow control is enabled, this pin will be configured as UART CTS.
18	VDDC	Power	Digital core power supply
19	VDDIO_0	Power	Digital I/O power supply
20	GPIO3	Digital I/O, Programmable Pull-up	General Purpose IO Port 3⁽¹⁾
21	GPIO4	Digital I/O, Programmable Pull-up	General Purpose IO Port 4⁽¹⁾
22	UART_TXD	Digital I/O, Programmable Pull-up	Wi-Fi UART TXD output Used only for debug development purposes Adding a test point for this pin is recommended
23	UART_RXD	Digital I/O, Programmable Pull-up	Wi-Fi UART RXD input Used only for debug development purposes Adding a test point for this pin is recommended
24	VBAT_BUCK	Power	Power supply pin for DC/DC converter
25	VSW	Power	Switching output of DC/DC Converter
26	VREG_BUCK	Power	Core power from DC/DC converter
27	CHIP_EN	Analog	PMU enable High level enables the module Low level enables the module in Power-Down mode Connect to a host output that defaults low at power-up If the host output is tri-stated, add a 1 MΩ pull-down resistor, if necessary, to ensure a low level at power-up
28	RTC_CLK	Digital I/O, Programmable Pull-up	RTC clock input Connect to a 32.768 kHz clock source
29	SD_CLK/GPIO_8	Digital I/O, Programmable Pull-up	SDIO clock line from the ATWILC3000A when the module is configured for SDIO
30	SD_CMD/SPI_SCK	Digital I/O, Programmable Pull-up	SDIO CMD line from ATWILC3000A when the module is configured for SDIO SPI clock from ATWILC3000A when the module is configured for SPI
31	SD_DAT0/SPI_MISO	Digital I/O, Programmable Pull-up	SDIO Data Line 0 from the ATWILC3000A when the module is configured for SDIO SPI MISO (Host In Client Out) pin from the ATWILC3000A when the module is configured for SPI
32	SD_DAT1/SPI_SSN	Digital I/O, Programmable Pull-up	SDIO Data Line 1 from the ATWILC3000A when the module is configured for SDIO Active-low SPI SSN (Client Select) pin from the ATWILC3000A when the module is configured for SPI
33	VDDIO_1	Power	Digital I/O power supply
34	SD_DAT2/SPI_MOSI	Digital I/O, Programmable Pull-up	SDIO Data Line 2 from the ATWILC3000A when the module is configured for SDIO SPI MOSI (Host Out Client In) pin from the ATWILC3000A when the module is configured for SPI
35	SD_DAT3/GPIO_7	Digital I/O, Programmable Pull-up	SDIO Data Line 3 from the ATWILC3000A when the module is configured for SDIO
36	GPIO17	Digital I/O, Programmable Pull-up	General Purpose I/O Port 17⁽¹⁾
37	GPIO18	Digital I/O, Programmable Pull-up	General Purpose I/O Port 18⁽¹⁾
38	GPIO19	Digital I/O, Programmable Pull-up	General Purpose I/O Port 19⁽¹⁾
39	GPIO20	Digital I/O, Programmable Pull-up	General Purpose I/O Port 20⁽¹⁾
40	IRQN	Digital I/O, Programmable Pull-up	ATWILC3000A interrupt output Connect to a host interrupt pin
41	GPIO21	Digital I/O, Programmable Pull-up	General Purpose I/O Port 21⁽¹⁾
42	GPIO0	Digital I/O, Programmable Pull-up	General Purpose I/O Port 0⁽¹⁾
43	XO_N	Analog	Crystal oscillator N
44	XO_P	Analog	Crystal oscillator P
45	VDD_SXDIG	Power	SX power supply
46	VDD_VCO	Power	VCO power supply
47	VDDIO_A	Power	Tuner VDDIO power supply
48	TP_P	Analog	Test pin/no connection
49	PADDLE VSS	Power	Connect to system board ground

Note:

Use of the GPIO functionality is not supported by the firmware. The data sheet will be updated once the support for this feature is added.