8.3 Power-up/Down Sequence

The following figure illustrates the power-up/down sequence for the ATWILC3000A.

Figure 8-2.  Power-up/Down Sequence

The following table provides power-up/down sequence timing parameters.

Table 8-3.  Power-up/Down Sequence Timing
ParameterMin.Max.UnitsDescriptionNotes
tA0—msVBAT rise to VDDIO riseVBAT and VDDIO can rise simultaneously or be connected together. VDDIO must not rise before VBAT.
tB0—msVDDIO rise to CHIP_EN riseCHIP_EN must not rise before VDDIO. CHIP_EN must be driven high or low and must not be left floating.
tC5—msCHIP_EN rise to RESETN riseThis delay is required to stabilize the XO clock before RESETN removal. RESETN must be driven high or low and must not be left floating.
tA’0—msVDDIO fall to VBAT fallVBAT and VDDIO fall simultaneously or are connected together. VBAT must not fall before VDDIO.
tB’0—msCHIP_EN fall to VDDIO fallVDDIO must not fall before CHIP_EN. CHIP_EN and RESETN must fall simultaneously.
tC’0—msRESETN fall to VDDIO fallVDDIO must not fall before RESETN. RESETN and CHIP_EN fall simultaneously.