8.4 Digital I/O Pin Behavior During Power-up Sequences
The following table represents the digital I/O pin states corresponding to the device power modes.
| Device State | VDDIO | CHIP_EN | RESETN | Output Driver | Input Driver | Pull-up/Down Resistor (96 kΩ) |
|---|---|---|---|---|---|---|
| Power_Down: Core Supply Off | High | Low | Low | Disabled (High-Z) | Disabled | Disabled |
| Power-on Reset: Core Supply and HardReset On | High | High | Low | Disabled (High-Z) | Disabled | Enabled |
| Power-on Default: Core Supply On, Device Out of Reset and Not Programmed | High | High | High | Disabled (High-Z) | Enabled | Enabled |
|
On_Doze/On_Transmit/ On_Receive: Core Supply On, Device Programmed by Firmware | High | High | High | Programmed by Firmware for Each Pin: Enabled or Disabled | Opposite of Output Driver State | Programmed by Firmware for Each Pin: Enabled or Disabled |