13.10 Device Identification

Device identification relies on the Arm CoreSight component identification scheme, which allows the chip to be identified as a SAM device implementing a DSU. The DSU contains identification registers to differentiate the device.

Note: During Coresight discovery (that allows a debugger to identify the available on-chip debug resources), the TPIU and ETB ROM table content (containing component and device IDs) read as 0. Debugger may conclude that TPIU and ETB are unavailable and indicate that trace is not available. A solution to that unexpected behavior is to set the TRCENA bit in the ARM Core Debug Exception and Monitor Control Register (DEMCR) before starting the Coresight discovery process.