34.7.1 Control A

This bit enables the SCL low time-out. If SCL is held low for 25ms-35ms, the Client will release its clock hold, if enabled, and reset the internal state machine. Any interrupt flags set at the time of time-out will remain set.

This bit is not synchronized.

This bit controls when SCL will be stretched for software interaction.

This bit is not synchronized.

These bits define bus speed.

These bits are not synchronized.

This bit enables the Client SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the Client will release its clock hold if enabled and reset the internal state machine. Any interrupt flags set at the time of time-out will remain set. If the address was recognized, PREC will be set when a STOP is received.

This bit is not synchronized.

These bits define the SDA hold time with respect to the negative edge of SCL.

These bits are not synchronized.

This bit sets the pin usage to either two- or four-wire operation:

This bit is not synchronized.

This bit defines the functionality in standby sleep mode.

This bit is not synchronized.

These bits must be written to 0x04 to select the I²C Client serial communication interface of the SERCOM.

These bits are not synchronized.

Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRL.ENABLE will read back immediately and the Enable Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.

This bit is not enable-protected.

Writing '0' to this bit has no effect.

Writing '1' to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SERCOM will be disabled.

Writing '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded. Any register write access during the ongoing reset will result in an APB error. Reading any register will return the reset value of the register.

Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.