20.5.3.3.3 Hibernate and Backup Mode

Hibernate mode and Backup mode allow achieving the lowest power consumption aside from OFF. The device is entirely powered off except for the backup domain. All peripherals in backup domain are allowed to run, for example, the RTC can be clocked by a 32.768 kHz oscillator. All PM registers are retained except INTENCLR, INTENSET, INTFLAG, and SLEEPCFG registers.

• Entering Hibernate or Backup mode: This mode is entered by executing the WFI instruction after selecting the Hibernate or Backup mode by writing the Sleep Mode bits in the Sleep Configuration register (SLEEPCFG20.6.2 Sleep Configuration.SLEEPMODE=HIBERNATE or =BACKUP).
• Exiting Hibernate or Backup mode: is triggered when a Hibernate or Backup Reset is detected by the Reset Controller (RSTC).
  Note: In Hibernate mode, the MAINVREG (in low-power mode) regulator is used to allow powering the PDRAM power domain which can be fully retained according to software configuration.
  Note: In Backup mode, the backup regulator (LPVREG) is used, unless VREG.RUNBKUP = 1. When VREG.RUNBKUP is set, the Main regulator is used in backup mode. The PDBKUPRAM power domain can be fully retained according to software configuration.

  Refer to the 20.5.3.5 Power Domain Controller for the RAM state.