33.6.6 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers must be synchronized when written or read.
The following bits are synchronized when written:
- The Software Reset bit in the CTRLA register (CTRLA.SWRST)
- The Enable bit in the CTRLA register (CTRLA.ENABLE)
- The Receiver Enable bit in the CTRLB register (CTRLB.RXEN)
Note: The CTRLB.RXEN is write-synchronized
somewhat differently. Refer to the CTRLB register for details.
Required write synchronization is denoted by the "Write-Synchronized" property in the register description.