29.6.5 PORT Access Priority

The PORT is accessed by different systems:

  • The Arm CPU through the high-speed matrix and the AHB/APB bridge (APB)

  • EVSYS through four asynchronous input events

The following priority is adopted:

  1. APB.
  2. EVSYS input events, except for events with EVCTRL.EVACTn = OUT, where the output pin follows the event input signal, independently of the OUT register value.
Note: One clock cycle latency can be observed on the APB access in case of concurrent PORT accesses.

For input events that require different actions on the same I/O pin, refer to 29.6.4 Events.