21.6.2.3 Reset Causes and Effects
The latest Reset cause is available in RCAUSE register, and can be read during the application boot sequence that followed the reset in order to determine proper action.
These are the groups of Reset sources:
- Power Supply Reset: Resets caused by an electrical issue. It covers POR and BODs Resets.
- User Reset: Resets caused by the application. It covers external Resets, system Reset requests and watchdog Resets.
- Backup Reset: Resets caused by a Backup Mode exit condition.
The following table lists the parts of the device that are reset, depending on the Reset type.
| Power Supply Reset | User Reset | ||
|---|---|---|---|
| POR, BOD33, BOD12 | External Reset | WDT Reset, System Reset Request, NVM Reset | |
| RTC, OSC32KCTRL, RSTC | Reset | - | - |
| GCLK with WRTLOCK | Reset | - | - |
| Debug logic | Reset | Reset | - |
| Others | Reset | Reset | Reset |
The external Reset is generated when pulling the RESET pin low.
The POR, BOD12, and BOD33 Reset sources are generated by their corresponding module in the Supply Controller Interface (SUPC).
The WDT Reset is generated by the Watchdog Timer.
The System Reset Request is a Reset generated by the CPU when asserting the SYSRESETREQ bit located in the Reset Control register of the CPU (for details refer to the ARM® Cortex™ Technical Reference Manual on http://www.arm.com).
The NVM Reset is a Reset generated by the NVMCTRL when for example a BKSWRST command is performed (for details refer to NVMCTRL chapter).
From Backup Mode, the chip can be waken-up upon these conditions:
- Battery Backup Power Switch (BBPS): generated by the SUPC controller when the 3.3V VDD is restored
- Real-Time Counter interrupt: For details refer to the applicable INTFLAG register in the RTC for details
If one of these conditions is triggered in Backup Mode, the RCAUSE.BACKUP bit is set and the Backup Exit Register (BKUPEXIT) is updated.