23.7.1 Control A in COUNT32 mode (CTRLA.MODE=0)
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection, Enable-Protected Bits, Write-Synchronized Bits |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| COUNTSYNC | BKTRST | PRESCALER[3:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MATCHCLR | MODE[1:0] | ENABLE | SWRST | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 15 – COUNTSYNC COUNT Read Synchronization Enable
This bit is not enable-protected.
Note: For
the first value read, read the COUNT register prior to enable the COUNT read
synchronization (COUNTSYNC = 0). After enabling the COUNT read synchronization
(COUNTSYNC = 1), read the COUNT register until its value is changed when
compared to its first value read. All subsequent COUNT values are then
valid.
| Value | Description |
|---|---|
| 0 | COUNT read synchronization is disabled |
| 1 | COUNT read synchronization is enabled |
Bit 13 – BKTRST BKUP Registers Reset On Tamper Enable
This bit is not synchronized.
| Value | Description |
|---|---|
| 0 | BKUPn registers will not reset when a tamper condition occurs. |
| 1 | BKUPn registers will reset when a tamper condition occurs. |
Bits 11:8 – PRESCALER[3:0] Prescaler
Note: When the tamper or
debouncing features (TAMPCTRL) are enabled, periodic interrupts and events are
generated even when the prescaler is OFF (CTRLA.PRESCALER = 0). In this specific
situation, clear the Periodic Interval n Event Output Enable bits (EVCTRL.PEREOn
= 0 [n = 7...0]) and respective Periodic Interval n Interrupt Enable
(INTENCLR.PERn = 1 [n =7...0]) bits.
| Value | Name | Description |
|---|---|---|
| 0x0 | OFF | CLK_RTC_CNT = GCLK_RTC/1 |
| 0x1 | DIV1 | CLK_RTC_CNT = GCLK_RTC/1 |
| 0x2 | DIV2 | CLK_RTC_CNT = GCLK_RTC/2 |
| 0x3 | DIV4 | CLK_RTC_CNT = GCLK_RTC/4 |
| 0x4 | DIV8 | CLK_RTC_CNT = GCLK_RTC/8 |
| 0x5 | DIV16 | CLK_RTC_CNT = GCLK_RTC/16 |
| 0x6 | DIV32 | CLK_RTC_CNT = GCLK_RTC/32 |
| 0x7 | DIV64 | CLK_RTC_CNT = GCLK_RTC/64 |
| 0x8 | DIV128 | CLK_RTC_CNT = GCLK_RTC/128 |
| 0x9 | DIV256 | CLK_RTC_CNT = GCLK_RTC/256 |
| 0xA | DIV512 | CLK_RTC_CNT = GCLK_RTC/512 |
| 0xB | DIV1024 | CLK_RTC_CNT = GCLK_RTC/1024 |
| 0xC-0xF | - | Reserved |
Bit 7 – MATCHCLR Clear on Match
This bit defines if the counter is cleared or not on a match.
This bit is not synchronized.
| Value | Description |
|---|---|
| 0 | The counter is not cleared on a Compare/Alarm 0 match |
| 1 | The counter is cleared on a Compare/Alarm 0 match |
Bits 3:2 – MODE[1:0] Operating Mode
This bit group defines the operating mode of the RTC.
This bit is not synchronized.
| Value | Name | Description |
|---|---|---|
| 0x0 | COUNT32 | Mode 0: 32-bit counter |
| 0x1 | COUNT16 | Mode 1: 16-bit counter |
| 0x2 | CLOCK | Mode 2: Clock/calendar |
| 0x3 | - | Reserved |
Bit 1 – ENABLE Enable
| Value | Description |
|---|---|
| 0 | The peripheral is disabled |
| 1 | The peripheral is enabled |
Bit 0 – SWRST Software Reset
Writing a ‘0’ to this bit has no effect.
Writing a '1' to this bit resets all registers in the RTC (except DBGCTRL) to their initial state, and the RTC will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded.
Due to synchronization there is a delay between writing CTRLA.SWRST and until the reset is complete. CTRLA.SWRST will be cleared when the reset is complete.
Note:
- When the CTRLA.SWRST is written, the user must poll the SYNCBUSY.SWRST bit to know when the reset operation is complete.
- During a SWRST, access to registers/bits without the SWRST are disallowed until the SYNCBUSY.SWRST is cleared by hardware.
| Value | Description |
|---|---|
| 0 | There is not reset operation ongoing |
| 1 | The reset operation is ongoing |