5.1 Power Supplies
The following table defines the power supply requirements of the PL460.
| Name | Associated Ground | Description |
|---|---|---|
| VDDCORE | GND | Core power supply with internal connection to 1.25V voltage regulator output. |
| VDDIO | GND | 3.3V Digital supply. |
| VDDIN | GND | 3.3V Input for core voltage regulator. |
| VDDIN_AN | AGND | 3.3V Analog supply (ADC + PGA). |
| VDDPLL | GND | 1.25V Voltage Regulator Output. To be connected to VDDCORE through a low-pass filter. |
| PVDDAMP | PGND | 8-16V Power supply of the embedded PLC driver |
| VDDAMP | GNDAMP | 3.3V Digital and analog supply of PLC driver |
The PL460 embeds a voltage regulator to supply the core. The Voltage Regulator state is controlled by the ENABLE pin. The VDDCORE pins in the package must be populated with external decoupling capacitors; connecting one 100 nF and one 2.2 µF capacitor to each pair of VDDCORE pins, C1-C2 and H5-J5, is recommended.
All ground pads GND, AGND and PGND must be connected at the PCB level. Furthermore, it is recommended to keep PGND and AGND nets in the PCB layout in separate power planes with a single point connection to GND. Refer to reference designs provided by Microchip for a reference layout.
Assuming previous described connections are done, the following decoupling capacitors are mandatory at the PCB level:
- MLCC 100 nF 10% 25V X7R 0603 between VREGN and GNDAMP
- MLCC 100 nF 10% 25V X7R 0603 between VREGP and VDD
- MLCC 100 nF 10% 25V X7R 0603 between VDDAMP and GND
PVDDAMP decoupling capacitive network is highly dependent on final application. Refer to 3 Signal Description for the recommended decoupling network for NB-PLC cases.