5.2 Power Constraints

The following power constraints apply to the PL460 device. Deviating from these constraints may lead to unwanted device behavior.

  • PVDDAMP must be stable when transmitting. A variation of 1V above or 2V below the configured PVDDAMP voltage can damage internal regulators and must be avoided. Microchip recommends to monitor PVDDAMP and, if the conditions described occurs, disable transmissions using pin TXEN.
  • VDDIN and VDDIO must have the same level, 3.3V.
  • VDDPLL voltage must be derived from VDDCORE through a low-pass filter. Using a second order LC with a cutoff frequency equal to 25 KHz is recommended. The inductor can be replaced by a ferrite bead, then a cutoff frequency equal to 75 KHz could be acceptable. In those cases, it is mandatory to check the communication performances of the system to detect problems originating from poor PLL supply filtering.
Figure 5-1. Core Voltage Regulator Connectivity(1)
Note:
  1. Refer to 3 Signal Description and reference designs provided by Microchip for further information about recommended values of decoupling capacitors and low-pass filter components.

For more information on power considerations, refer to 11.8 Power On Considerations.