3 Signal Description

Table 3-1. Signal Description List
Signal Name	Function	Type	Active Level	Voltage Reference	Comments
Power Supplies
VDDIO	3.3V Digital supply	Power	—	—	3.0V to 3.6V ^{(Note 1)}
VDDIN	3.3V Voltage input for core voltage regulator	Power	—	—	3.0V to 3.6V ^{(Note 1)}
VDDIN_AN	3.3V Analog supply (ADC + PGA)	Power	—	—	3.0V to 3.6V ^{(Note 2)}
VDDCORE	1.25V Voltage Regulator Output with internal connection to Core power supply	Power	—	—	1.25V ^{(Note 3)}
VDDPLL	1.25V PLL power supply input. Must be connected to VDDCORE through a LP filter	Power	—	—	1.25V ^{(Note 4)}
VREGP	PLC Driver voltage regulator output for external decoupling capacitor	Power	—	—	^{(Note 5)}
VREGN	PLC Driver voltage regulator output for external decoupling capacitor	Power	—	—	^{(Note 6)}
PVDDAMP	Power supply of PLC driver amplifier and regulators	Power	—	—	8V to 16V ^{(Note 7,}⁸⁾
VDDAMP	3.3V Digital and analog power supply of PLC driver	Power	—	—	3.0 to 3.6V ^{(Note 9)}
GND	Digital ground	Power	—	—	^{(Note 10)}
AGND	Analog ground	Power	—	—	^{(Note 10)}
PGND	Power ground of PLC driver	Power	—	—	^{(Note 10)}
GNDAMP	Analog ground of PLC driver	Power	—	—	^{(Note 10)}
Clocks, Oscillators and PLLs
XIN	Crystal Oscillator Input	Input	—	VDDIO	—
XOUT	Crystal Oscillator Output	Output	—	VDDIO	—
Reset/Enable
NRST	System Reset	Input	Low	VDDIO	^{(Note 11)}
ENABLE	Enable Internal core voltage regulator	Input	High	VDDIO	—
Power Line Communications
OUT	Switching amplifier output	Output	—	PVDDAMP	—
ASO[0:1]	Analog Switch Outputs to disable the bandpass filtering when there is no PLC transmission activity	Output	—	PVDDAMP	High-voltage, high-current, and low resistance analog switches.
ASI[0:1]	Analog Switch status	Output	—	VDDIO	—
VIN	PLC signal reception input	Input	—	VDDIN_AN	—
AGC	Automatic Gain Control. This digital tri-state output is managed by AGC hardware logic to drive external circuitry when input signal attenuation is needed	Output	—	VDDIO	^{(Note 12)}
VZC	Mains Zero-Cross Detection Signal. This input detects the zero-crossing of the mains voltage	Input	—	VDDIO	External Protection Resistor ^{(Note 12,}¹³⁾
VREFP	Internal Reference “Plus” Voltage	Analog	—	VDDIN_AN	^{(Note 14)}
VREFN	Internal Reference “Minus” Voltage	Analog	—	VDDIN_AN	^{(Note 14)}
VREFC	Internal Reference Common-mode Voltage	Analog	—	VDDIN_AN	^{(Note 15)}
EMIT[2:3]	PLC Tri-state Transmission ports	Output	—	VDDIO	—
TXRX1	Analog Front-End Transmission/Reception for the auxiliary transmission branch. This digital output is used to modify external coupling behavior in Transmission/Reception	Output	—	VDDIO	—
Input/Output
STBY	Enable Sleep mode of the modem	Input	High	VDDIO	^{(Note 16)}
EXTIN	Indication of pending events	Output	Low	VDDIO	—
TXEN	Transmission enabled	Input	High	VDDIO	—
Thermal Monitor
THEN	Enable Thermal Monitor functionality	Input	High	VDDIO	—
NTHW0	Indication of the first thermal warning	Output	—	VDDIO	—
THW1	Indication of the second thermal warning	Output	—	VDDIO	—
G1	General Purpose Input	Input	High	VDDIO	—
Serial Peripheral Interface - SPI
CS	SPI Chip Select	Input	Low	VDDIO	Internal pull up ^{(Note 17)}
SCK	SPI Clock signal	Input	—	VDDIO	Internal pull up ^{(Note 17)}
MOSI	SPI Host Out Client In	Input	—	VDDIO	Internal pull up ^{(Note 17)}
MISO	SPI Host In Client Out	Output	—	VDDIO	—

Notes:

Connecting two 100 nF decoupling multilayer ceramic capacitors (MLCC) to the VDDIO and VDDIN pins is recommended. In addition, for correct PLC transmission using the auxiliary branch, placing one 4.7 μF decoupling multilayer ceramic capacitor (MLCC) as close as possible to VDDIO pins, D1 and D3, is strongly recommended.
Placing a 100 nF decoupling multilayer ceramic capacitor (MLCC) in the VDDIN_AN pins is recommended.
Placing 100 nF plus 2.2 μF decoupling multilayer ceramic capacitors (MLCC) in each pair of VDDCORE pins (H5-J5 and C1-C2) is recommended.
Placing 100 nF plus 4.7 μF decoupling multilayer ceramic capacitors (MLCC) in the VDDPLL pin is recommended.
A 100 nF multilayer ceramic capacitor (MLCC) is required between the VREGP and PVDDAMP pads for decoupling and stabilization purposes.
A 100 nF multilayer ceramic capacitor (MLCC) is required between the VREGN and GNDAMP pads for decoupling and stabilization purposes.
Placing one 100 uF aluminum Low-ESR 25V capacitor and three 100 nF 25V multilayer ceramic capacitors (MLCC) in the PVDDAMP pins is recommended.
The PLC-protocol firmwares provided by Microchip are configured by default for a power supply of the PLC driver amplifier of 12V.
Placing a 100 nF decoupling multilayer ceramic capacitor (MLCC) in the VDDAMP pins is recommended.
Separate pins are provided for GND, AGND, PGND, and GNDAMP grounds. Taking these layout considerations into account to reduce interference is recommended. It is recommended to connect ground pins as short as possible to the system ground plane. For more details about EMC Considerations, refer to AVR040 Application Note.
It is recommended to connect the NRST signal to a GPIO in the host controller with an internal pull-down default reset configuration to help keep PL460 in reset until the host boots. For more details, refer to Reset (NRST) Pin.
See Table 11-4.
VZC is not isolated; some isolation circuitry is required in case of using a non-isolated design. Refer to the reference design for additional information.
Bypass to analog ground with an external 22 nF decoupling capacitor and connect an external 10 nF decoupling capacitor between VREFP and VREFN.
Bypass to analog ground with an external 10 nF decoupling capacitor.
The STBY signal must be connected to GND if the Sleep mode functionality is not used. If using the Sleep mode functionality, the STBY signal must be connected to a GPIO in the host controller with an internal pull-down default reset configuration to avoid enabling Sleep mode until the host boots. For more details, refer to Standby (STBY) Pin.
See Table 11-5.