4.5.2.1 Support FIFO Overview

The Support FIFO (SFIFO) is a 16-byte deep register bank that stores data with first-in-first-out functionality. The SFIFO has two read and two write interfaces:

  • AVR bus read and write access
  • Direct write access from the RSSI buffer
  • Direct read access not connected in ATA8210/15

Furthermore, the SFIFO implements a configurable fill-level status bit with maskable interrupt signaling. Read attempts to an empty SFIFO (underflow) and write attempts to a full SFIFO (overflow) are indicated by error flags (SFS.SFUFL and SFS.SFOFL) in the user interface. An error IRQ is triggered if masked in SFI.SFERIM.

The following figure shows a block diagram of the SFIFO.
Figure 4-23. SFIFO Block Diagram

The access mode of the SFIFO is configured by the SFC.SFDRA register bit. If the bit is set to ‘0’, the RSSI buffer can write to the SFIFO via the direct write interface while the AVR can only read from the SFIFO. This mode must be selected if the ATA8210/15 is receiving data. If the SFC.SFDRA bit is set to ‘1’, the AVR can only write to the SFIFO.

The SFIFO can trigger an interrupt if a certain fill level is reached. The interrupt can be switched on by setting the support FIFO fill-level interrupt mask bit (SFI.SFFLIM) to ‘1’. The required fill level can be configured in the SFIFO fill level configuration register (SFC.SFFLC) to any value between 0 and 16. Once the configured fill level is reached (in SFDRA = 0 mode after a byte was written to the SFIFO, in SFDRA = 1 mode after a byte was read from the SFIFO), the SFIFO fill level reached status bit (SFS.SFFLRF) is set and the interrupt is triggered if enabled.

The current fill level can be read at any time in the SFIFO fill level register (SFL.SFFLS).

The AVR can access the data in the SFIFO by writing or reading the SFIFO data register (SFD). The user has to set the SFC.SFDRA correctly to allow either a write or a read access by the AVR.

The current read and write pointer addresses can be read from the SFRP and SFWP registers, respectively. The AVR also has write access to these registers, but manual pointer manipulations must be handled with care and are mainly implemented for debugging purposes.

The SFIFO is reset when activated in the corresponding power reduction register PRR2.PRSF or by writing a ‘1’ to the SFL.SFCLR bit. See Sleep Modes and Active Power Reduction from Related Links.

For more details on the description of the required register bits, see Support FIFO Register Description from Related Links.