39.16 TWI

Figure 39-7. TWI - Timing Requirements
Table 39-22. TWI - Timing Specifications
Symbol Description Min. Typ.✝ Max. Unit Condition
VDD Supply voltage range 1.8 — 5.5 V fSCL ≤ 400 kHz
2.2 * — 5.5 * fSCL ≤ 1 MHz
fSCL * SCL clock frequency — — 1000 kHz Max. frequency requires system clock at 10 MHz
VHYS * Hysteresis of Schmitt Trigger inputs 0.05×VDD 0.4×VDD V
VOL Output low voltage — — 0.4 V Iload = 5 mA, VDD > 2V
— — 0.2×VDD Iload = 3 mA, VDD ≤ 2V
IOL * Low-level output current 5 — — mA VOL = 0.4V
10 — — VOL = 0.4V

VDD ≥ 2.7V
CB * Capacitive load for each bus line — — 400 pF fSCL ≤ 100 kHz
— — 400 fSCL ≤ 400 kHz
— — 550

fSCL ≤ 1 MHz

VDD > 2.75V
tR * Rise time for both SDA and SCL — — 1000 ns fSCL ≤ 100 kHz
20 — 300 fSCL ≤ 400 kHz
— — 120 fSCL ≤ 1 MHz
tOF * Output fall time from VIHmin to VILmax — — 250 ns

fSCL ≤ 100 kHz

10 pF < CB < 400 pF
20×(VDD/5.5V) — 250

fSCL ≤ 400 kHz

10 pF < CB < 400 pF
20×(VDD/5.5V) — 120

fSCL ≤ 1 MHz

10 pF < CB < 400 pF
tSP * Spikes suppressed by the input filter 0 — 50 ns
IL * Input current for each I/O pin — — 1 µA 0.1×VDD < VI < 0.9×VDD
CI * Capacitance for each I/O pin — — 10 pF
RP * Value of pull-up resistor (VDD-VOL(max)) /IOL — 1000 ns/(0.8473×CB) Ω fSCL ≤ 100 kHz
(VDD-VOL(max)) /IOL — 300 ns/(0.8473×CB) fSCL ≤ 400 kHz
(VDD-VOL(max)) /IOL — 120 ns/(0.8473×CB) fSCL ≤ 1 MHz
tHD_STA * Hold time (repeated) Start condition 4.0 — — µs fSCL ≤ 100 kHz
0.6 — — fSCL ≤ 400 kHz
0.26 — — fSCL ≤ 1 MHz
TLOW * Low period of SCL Clock 4.7 — — µs fSCL ≤ 100 kHz
0.6 — — fSCL ≤ 400 kHz
0.35 — — fSCL ≤ 1 MHz
THIGH * High period of SCL Clock 4.0 — — µs fSCL ≤ 100 kHz
0.6 — — fSCL ≤ 400 kHz
0.26 — — fSCL ≤ 1 MHz
tSU_STA * Setup time for a repeated Start condition 4.7 — — µs fSCL ≤ 100 kHz
0.6 — — fSCL ≤ 400 kHz
0.26 — — fSCL ≤ 1 MHz
tHD_DAT * Data hold time across all corners — 0 — ns SDAHOLD[1:0] = 0x0
300 — 900 SDAHOLD[1:0] = 0x3
tSU_DAT * Data setup time 250 — — ns fSCL ≤ 100 kHz
100 — — fSCL ≤ 400 kHz
50 — — fSCL ≤ 1 MHz
tSU_STO * Setup time for Stop condition 4 — — µs fSCL ≤ 100 kHz
0.6 — — fSCL ≤ 400 kHz
0.26 — — fSCL ≤ 1 MHz
tBUF * Bus free time between a Stop and Start condition 4.7 — — µs fSCL ≤ 100 kHz
1.3 — — fSCL ≤ 400 kHz
tCS * Client Clock Stretching delay — — 250 ns

✝ Data found in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only.

* These parameters are characterized but not tested in production.