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AVR® Instruction Set Manual
AVR® Instruction Set Manual
  1. Home
  2. 8 Revision History
  3. 8.7 Rev.0856I – 07/2010

  • Introduction
  • 1 Instruction Set Nomenclature
  • 2 CPU Registers Located in the I/O Space
  • 3 The Program and Data Addressing Modes
  • 4 Conditional Branch Summary
  • 5 Instruction Set Summary
  • 6 Instruction Description
  • 7 Appendix A Device Core Overview
  • 8 Revision History
    • 8.1 Rev. DS40002198C - 11/2024
    • 8.2 Rev. DS40002198B - 02/2021
    • 8.3 Rev. DS40002198A - 05/2020
    • 8.4 Rev.0856L - 11/2016
    • 8.5 Rev.0856K - 04/2016
    • 8.6 Rev.0856J - 07/2014
    • 8.7 Rev.0856I – 07/2010
    • 8.8 Rev.0856H – 04/2009
    • 8.9 Rev.0856G – 07/2008
    • 8.10 Rev.0856F – 05/2008
  • Legal Disclaimer
  • Microchip Information

8.7 Rev.0856I – 07/2010

1. Updated section "Instruction Set Summary" with new instructions: LAC, LAS, LAT, and XCH.

Section "LAC - Load and Clear"

Section "LAS – Load and Set"

Section "LAT – Load and Toggle"

Section "XCH – Exchange"

2. Updated number of clock cycles column to include Reduced Core tinyAVR.

(ATtiny replaced by Reduced Core tinyAVR).

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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