1.7.2 Private Read Transaction
The user firmware/DMA writes the data byte to the I3CxTXB register, which feeds into the Transmit FIFO. Once the Private Read request is ACK’d, the Target starts sending the 9-bit data words (8-bit data byte + 1-bit End-of-Data T-bit) from the Transmit FIFO onto the bus. The transaction completes when either the Target or the controller ends the transaction as described below, followed by a Restart or a Stop, which is represented using the Transaction Complete TCOMPIF flag:
- The Target pulls the End-of-Data T-bit low after the Transmit FIFO becomes empty and all the data has been sent
- The controller aborts the transaction prematurely by pulling the End-of-Data T-bit low (a Restart condition on the bus), and the Abort Error ABEIF flag is set
The flags on Table 1-2 provide additional buffer management abilities to the user.
| Flag | Description | |
|---|---|---|
| TXBE | Transmit Buffer Empty | The I3CxTXB register is empty and ready to be written |
| I3CxTXIF | Transmit Interrupt | System level interrupt for TXBE condition notifying the firmware/DMA to write the data to the I3CxTXB register |
| CLRTXB | Clear Transmit Buffer + FIFO | Command to clear the I3CxTXB register and reset the Transmit FIFO |
| TXWEIF | Transmit Write Error | Error interrupt signifying an attempt to write to the I3CxTXB
register when an existing data has not yet been moved to the Transmit
FIFO (TXBE = 0) |
| TXUIF | Transmit Underrun Error | Error interrupt signifying that a read request has been made by the controller when the Transmit FIFO is empty |
| TXFNE | Transmit FIFO Not Empty | The Transmit FIFO (excludes the I3CxTXB register) status |