1.7.1 Private Write Transaction
Once the Private Write request is ACK’d, the controller starts sending the 9-bit data words (8-bit data byte + 1-bit Parity T-bit). The received data bytes are stored in the Receive FIFO, which feeds into the I3CxRXB register for the user firmware/DMA to read. The transaction is completed when the controller sends a Stop or a Restart following the data, which is represented using the Transaction Complete TCOMPIF flag.
The flags on Table 1-1 provide additional buffer management abilities to the user.
| Flag | Description | |
|---|---|---|
| RXBF | Receive Buffer Full | Data are available in the I3CxRXB register and ready to be read |
| I3CxRXIF | Receive Interrupt | System level interrupt for RXBF condition notifying the firmware/DMA to read the data from the I3CxRXB register |
| CLRRXB | Clear Receive Buffer + FIFO | Command to clear the I3CxRXB register and reset the Receive FIFO |
| RXREIF | Receive Read Error | Error interrupt signifying an attempt to read from the I3CxRXB
register when data is not yet available from the Receive FIFO (RXBF =
0) |
| RXOIF | Receive Overrun Error | Error interrupt signifying that a data byte has been lost due to controller writing to an already full Receive FIFO |