25.10.4 CLB Clock Selection

Name:	CLBCLK
Offset:	0x00C3


Bit	7	6	5	4	3	2	1	0
	CLKSEL[3:0]				CLKPRE[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:4 – CLKSEL[3:0] CLB Clock Selection

Table 25-3. CLBCLK Clock Selections
Value	Description
`1111`	TMR1_overflow_OUT
`1110`	TMR0_overflow_OUT
`1101`	SOSC
`1100`	ADCRC
`1011`	EXTOSC
`1010`	LFINTOSC
`1001`	HFINTOSC
`1000`	F_OSC
`0111-0001`	Reserved
`0000`	CLBCLKPPS

Bits 3:0 – CLKPRE[3:0] CLB Clock Prescaler

Table 25-4. CLB Clock Prescaler Selections
Value	Dscription
`1111-1011`	Reserved
`1010`	1024
`1001`	512
`1000`	256
`0111`	128
`0110`	64
`0101`	32
`0100`	16
`0011`	8
`0010`	4
`0001`	2
`0000`	1

DS40002671A

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.