23.7.7 Synchronization Busy in COUNT16 mode (CTRLA.MODE=1)
Name: | SYNCBUSY |
Offset: | 0x10 |
Reset: | 0x00000000 |
Property: | - |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
Access | |||||||||
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
GP1 | GP0 | ||||||||
Access | R/W | R/W | |||||||
Reset | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
COUNTSYNC | |||||||||
Access | R | ||||||||
Reset | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
COMP1 | COMP0 | PER | COUNT | FREQCORR | ENABLE | SWRST | |||
Access | R/W | R/W | R | R | R | R | R | ||
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 16, 17 – GPn General Purpose n
Bit 15 – COUNTSYNC Count Read Sync Enable Synchronization Busy Status
Value | Description |
---|---|
0 | Write synchronization for CTRLA.COUNTSYNC bit is complete. |
1 | Write synchronization for CTRLA.COUNTSYNC bit is ongoing. |
Bits 5, 6 – COMPx Compare x Synchronization Busy Status [x = 1..0]
Value | Description |
---|---|
0 | Write synchronization for COMPx register is complete. |
1 | Write synchronization for COMPx register is ongoing. |
Bit 4 – PER Period Synchronization Busy Status
Value | Description |
---|---|
0 | Write synchronization for PER register is complete. |
1 | Write synchronization for PER register is ongoing. |
Bit 3 – COUNT Count Value Synchronization Busy Status
Value | Description |
---|---|
0 | Read/write synchronization for COUNT register is complete. |
1 | Read/write synchronization for COUNT register is ongoing. |
Bit 2 – FREQCORR Frequency Correction Synchronization Busy Status
Value | Description |
---|---|
0 | Write synchronization for FREQCORR register is complete. |
1 | Write synchronization for FREQCORR register is ongoing. |
Bit 1 – ENABLE Enable Synchronization Busy Status
Value | Description |
---|---|
0 | Write synchronization for CTRLA.ENABLE bit is complete. |
1 | Write synchronization for CTRLA.ENABLE bit is ongoing. |
Bit 0 – SWRST Software Reset Synchronization Busy Status
Value | Description |
---|---|
0 | Write synchronization for CTRLA.SWRST bit is complete. |
1 | Write synchronization for CTRLA.SWRST bit is ongoing. |