30.6.6 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read.
The following bits are synchronized when written:
- The Software Reset bit in the CTRLA register (CTRLA.SWRST)
- The Enable bit in the CTRLA register (CTRLA.ENABLE)
- The Receiver Enable bit in the CTRLB register (CTRLB.RXEN)
- The Transmitter Enable bit in the Control B register (CTRLB.TXEN)
Note: CTRLB.RXEN is write-synchronized somewhat
differently. See also CTRLB30.7.2 Control B for details.
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.