17.6.5 VDD Brown-Out Detector (BODVDD) Control

Name: BODVDD
Offset: 0x10
Reset: X determined from NVM User Row
Property: Write-Synchronized Bits, Enable-Protected Bits, PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
   LEVEL[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset xxxxxx 
Bit 15141312111098 
 PSEL[3:0]   ACTCFG 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 76543210 
  RUNSTDBYSTDBYCFGACTION[1:0]HYSTENABLE  
Access R/WR/WR/WR/WR/WR/W 
Reset 00xxxx 

Bits 21:16 – LEVEL[5:0]  BODVDD Threshold Level on VDD

These bits set the triggering voltage threshold for the BODVDD when the BODVDD monitors the VDD.

These bits are loaded from NVM User Row at start-up. The use of the HYST setting can help in eliminating restarts at startup when observed.

Note: This bit field is enable-protected. This bit field is not synchronized.

Bits 15:12 – PSEL[3:0] Prescaler Select

Selects the prescaler divide-by output for the BODVDD sampling mode. The input clock comes from the OSCULP32K 1.024 kHz output.

Note: This bit field is enable-protected. This bit field is not synchronized.
ValueNameDescription
0x0 DIV2 Divide clock by 2
0x1 DIV4 Divide clock by 4
0x2 DIV8 Divide clock by 8
0x3 DIV16 Divide clock by 16
0x4 DIV32 Divide clock by 32
0x5 DIV64 Divide clock by 64
0x6 DIV128 Divide clock by 128
0x7 DIV256 Divide clock by 256
0x8 DIV512 Divide clock by 512
0x9 DIV1024 Divide clock by 1024
0xA DIV2048 Divide clock by 2048
0xB DIV4096 Divide clock by 4096
0xC DIV8192 Divide clock by 8192
0xD DIV16384 Divide clock by 16384
0xE DIV32768 Divide clock by 32768
0xF DIV65536 Divide clock by 65536

Bit 8 – ACTCFG  BODVDD Configuration in Active Mode

Note: This bit is enable-protected. This bit is not synchronized.
ValueDescription
0 In active mode, the BODVDD operates in continuous mode.
1 In active mode, the BODVDD operates in sampling mode.

Bit 6 – RUNSTDBY Run in Standby

Note: This bit is enable-protected. This bit is not synchronized.
ValueDescription
0 In standby sleep mode, the BODVDD is disabled.
1 In standby sleep mode, the BODVDD is enabled.

Bit 5 – STDBYCFG  BODVDD Configuration in Standby Sleep Mode

If the RUNSTDBY bit is set to '1', the STDBYCFG bit sets the BODVDD configuration in standby sleep mode.

Note: This bit is enable-protected. This bit is not synchronized.
ValueDescription
0 In standby sleep mode, the BODVDD is configured in continuous mode.
1 In standby sleep mode, the BODVDD is configured in sampling mode.

Bits 4:3 – ACTION[1:0]  BODVDD Action

These bits are used to select the BODVDD action when the supply voltage crosses below the BODVDD threshold.

These bits are loaded from NVM User Row at start-up.

Note: This bit field is enable-protected. This bit field is not synchronized.
Value Name Description
0x0 NONE No action
0x1 RESET The BODVDD generates a reset
0x2 INT The BODVDD generates an interrupt
0x3 - Reserved

Bit 2 – HYST Hysteresis

This bit indicates whether hysteresis is enabled for the BODVDD threshold voltage.

This bit is loaded from NVM User Row at start-up.

Note: This bit is enable-protected. This bit is not synchronized.
ValueDescription
0 No hysteresis.
1 Hysteresis enabled.

Bit 1 – ENABLE Enable

This bit is loaded from NVM User Row at start-up.

Note:
  1. This bit is write-synchronized: STATUS.BVDDSRDY must be checked to ensure the BODVDD.ENABLE synchronization is complete.
  2. This bit is not enable-protected.
ValueDescription
0 BODVDD is disabled.
1 BODVDD is enabled.