17.6.5 VDD Brown-Out Detector (BODVDD) Control

Name: BODVDD
Offset: 0x10
Reset: X determined from NVM User Row
Property: Write-Synchronized Bits, Enable-Protected Bits, PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
   LEVEL[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset xxxxxx 
Bit 15141312111098 
 PSEL[3:0]   ACTCFG 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 76543210 
  RUNSTDBYSTDBYCFGACTION[1:0]HYSTENABLE  
Access R/WR/WR/WR/WR/WR/W 
Reset 00xxxx 

Bits 21:16 – LEVEL[5:0]  BODVDD Threshold Level on VDD

These bits set the triggering voltage threshold for the BODVDD when the BODVDD monitors the VDD.

These bits are loaded from NVM User Row at start-up. The use of the HYST setting can help in eliminating restarts at startup when observed.

Note: This bit field is enable-protected. This bit field is not synchronized.

Bits 15:12 – PSEL[3:0] Prescaler Select

Selects the prescaler divide-by output for the BODVDD sampling mode. The input clock comes from the OSCULP32K 1.024 kHz output.

Note: This bit field is enable-protected. This bit field is not synchronized.
ValueNameDescription
0x0DIV2Divide clock by 2
0x1DIV4Divide clock by 4
0x2DIV8Divide clock by 8
0x3DIV16Divide clock by 16
0x4DIV32Divide clock by 32
0x5DIV64Divide clock by 64
0x6DIV128Divide clock by 128
0x7DIV256Divide clock by 256
0x8DIV512Divide clock by 512
0x9DIV1024Divide clock by 1024
0xADIV2048Divide clock by 2048
0xBDIV4096Divide clock by 4096
0xCDIV8192Divide clock by 8192
0xDDIV16384Divide clock by 16384
0xEDIV32768Divide clock by 32768
0xFDIV65536Divide clock by 65536

Bit 8 – ACTCFG  BODVDD Configuration in Active Mode

Note: This bit is enable-protected. This bit is not synchronized.
ValueDescription
0In active mode, the BODVDD operates in continuous mode.
1In active mode, the BODVDD operates in sampling mode.

Bit 6 – RUNSTDBY Run in Standby

Note: This bit is enable-protected. This bit is not synchronized.
ValueDescription
0In standby sleep mode, the BODVDD is disabled.
1In standby sleep mode, the BODVDD is enabled.

Bit 5 – STDBYCFG  BODVDD Configuration in Standby Sleep Mode

If the RUNSTDBY bit is set to '1', the STDBYCFG bit sets the BODVDD configuration in standby sleep mode.

Note: This bit is enable-protected. This bit is not synchronized.
ValueDescription
0In standby sleep mode, the BODVDD is configured in continuous mode.
1In standby sleep mode, the BODVDD is configured in sampling mode.

Bits 4:3 – ACTION[1:0]  BODVDD Action

These bits are used to select the BODVDD action when the supply voltage crosses below the BODVDD threshold.

These bits are loaded from NVM User Row at start-up.

Note: This bit field is enable-protected. This bit field is not synchronized.
ValueNameDescription
0x0NONENo action
0x1RESETThe BODVDD generates a reset
0x2INTThe BODVDD generates an interrupt
0x3-Reserved

Bit 2 – HYST Hysteresis

This bit indicates whether hysteresis is enabled for the BODVDD threshold voltage.

This bit is loaded from NVM User Row at start-up.

Note: This bit is enable-protected. This bit is not synchronized.
ValueDescription
0No hysteresis.
1Hysteresis enabled.

Bit 1 – ENABLE Enable

This bit is loaded from NVM User Row at start-up.

Note:
  1. This bit is write-synchronized: STATUS.BVDDSRDY must be checked to ensure the BODVDD.ENABLE synchronization is complete.
  2. This bit is not enable-protected.
ValueDescription
0BODVDD is disabled.
1BODVDD is enabled.