16.5.3.3 Sleep Mode Controller

A Sleep mode is entered by executing the Wait For Interrupt instruction (WFI). The Sleep Mode bits in the Sleep Configuration register (SLEEPCFG.SLEEPMODE) select the level of the Sleep mode.

Note: A small latency happens between the store instruction and actual writing of the SLEEPCFG register due to bridges. Software must ensure that the SLEEPCFG register reads the desired value before issuing a WFI instruction.

Table 16-1. Sleep Mode Entry and Exit Table
Mode	Mode Entry	Wake-Up Sources
IDLE	SLEEPCFG.SLEEPMODE = IDLE	Synchronous ⁽²⁾, asynchronous ⁽¹⁾
STANDBY	SLEEPCFG.SLEEPMODE = STANDBY	Synchronous⁽³⁾, Asynchronous⁽¹⁾

Note:

Asynchronous: interrupt generated on GCLK generic clock, external clock, or external event.
Synchronous: interrupt generated on the APB clock.
Synchronous interrupt only for peripherals configured to run in standby.

Note: The type of wake-up sources (synchronous or asynchronous) is given in each module interrupt section.

The sleep modes (idle, standby) and their effect on the clocks activity, the regulator and the SRAM state are described in the table and the sections below.

Table 16-2. Sleep Mode Overview
Mode	CPU clock	AHB/APB clocks	Main clock	GCLK0 clock	GCLK1-8 clocks	Clock Sources		Regulator	SRAM
Mode	CPU clock	AHB/APB clocks	Main clock	GCLK0 clock	GCLK1-8 clocks	ONDEMAND = 0	ONDEMAND = 1	Regulator	SRAM
IDLE	Stop	Run⁽¹⁾	Run	Run	Run/Stop ⁽²⁾	Run	Run/Stop ⁽³⁾	Main	Normal
STANDBY	Stop	Stop⁽⁴⁾	Stop ⁽⁴⁾	Stop if RUNSTDBY = 0		Stop if RUNSTDBY = 0		LPVREG ⁽⁷⁾	Low Power ⁽⁸⁾
STANDBY	Stop	Stop⁽⁴⁾	Stop ⁽⁴⁾	Stop/Run if RUNSTDBY = 1 ⁽⁵⁾		Run if RUNSTDBY = 1	Stop/Run if RUNSTDBY = 1 ⁽⁶⁾	LPVREG ⁽⁷⁾	Low Power ⁽⁸⁾

Note:

The AHB/APB clocks are running up to MCLK, and then provided only to the IPs requesting them. For the other IPs not requesting the clocks, they are gated at MCLK output.
Each GCLK1 to GCLK8 is running if the associated generated clock is requested by at least one IP. It is stopped if no IP is requesting this clock.
The clock source is running if the clock is requested by at least one GCLK Generator. It is stopped if no GCLK Generator is requesting this clock and will be restarted as soon as an IP requests a clock coming from a GCLK fed by this clock source.
The AHB/APB clocks are stopped, except if requested by at least one IP, and in this case, only provided to this/these IP(s) through GCLK0 and MCLK.
Each GCLK generators is stopped, except if the clock it generates is requested by at least one IP.
Each Clock Source is stopped, except if the clock it generates is requested by at least one GCLK Generator.
Regulator state is programmable by using STDBYCFG.VREGSMOD bits.
SRAM state is programmable by using STDBYCFG.BBIASHS bit.