The processor provides debug
through registers in the SCS. Refer to the Cortex-M0+ Technical Reference
Manual for details (www.arm.com).
Nested Vectored Interrupt Controller
(NVIC)
External interrupt signals connect
to the NVIC, and the NVIC prioritizes the interrupts. Software can set the
priority of each interrupt. The NVIC and the Cortex-M0+ processor core are closely
coupled, providing low latency interrupt processing and efficient processing of
late arriving interrupts. Refer to 9.2 Nested Vector Interrupt Controller and Cortex-M0+ Technical Reference Manual for details
(www.arm.com).
System Timer (SysTick)
The System Timer is a 24-bit timer
clocked by CLK_CPU that extends the functionality of both the processor and the
NVIC. Refer to Cortex-M0+ Technical Reference Manual for details (www.arm.com). When the SysTick
Overflow Interrupt is enabled, the RAM Back Bias Control must be disabled
(PM->STDBYCFG.bit.BBIASHS = 0) before entering Standby Sleep mode.
System Control Block (SCB)
The System Control Block provides
system implementation information, and system control. This includes
configuration, control, and reporting of the system exceptions. Refer to
Cortex-M0+ Devices Generic User Guide for details (www.arm.com).
Micro Trace Buffer (MTB)
The CoreSight MTB-M0+ (MTB)
provides a simple execution trace capability to the Cortex-M0+ processor. Refer to
the section 9.3 Micro Trace Buffer and CoreSight MTB-M0+ Technical Reference Manual for
details (www.arm.com).
Memory Protection Unit (MPU)
The Memory Protection Unit divides
the memory map into a number of regions, and defines the location, size, access
permissions and memory attributes of each region. Refer to Cortex-M0+ Devices
Generic User Guide for details (http://www.arm.com)
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
