27.6.5 PORT Access Priority

The PORT is accessed by the following systems:

  • The Arm CPU through the Arm single-cycle I/O port (IOBUS)
  • The Arm CPU through the high-speed matrix and the AHB/APB bridge (APB)
  • EVSYS through four asynchronous input events

The CPU local bus (IOBUS) is an interface that connects the CPU to the PORT. It is a single-cycle bus interface, which does not support wait states. It supports 8-bit, 16-bit and 32-bit sizes.

This bus is generally used for low-latency operation. The Data Direction (DIR) and Data Output Value (OUT) registers can be read, write, set, cleared or toggled using this bus, and the Data Input Value (IN) registers can be read.

Because the IOBUS cannot wait for the IN register resynchronization, the Control register (CTRL) must be configured to continuous sampling of all pins that need to be read through the IOBUS to prevent stale data from being read.

IOBUS writes are not prevented to PAC write-protected registers when the PORT module is PAC protected.

Note: Refer to 7 Product Mapping for the PORT IOBUS address.

The following priority is adopted:

  1. Arm CPU IOBUS (No wait tolerated)
  2. APB
  3. EVSYS input events, except for events with EVCTRL.EVACTx = OUT, where the output pin follows the event input signal, independently of the OUT register value.
Note: One clock cycle latency can be observed on the APB access in case of concurrent PORT accesses.

For input events that require different actions on the same I/O pin, refer to 27.6.4 Events.