23.8.7 Synchronization Busy in Clock/Calendar mode (CTRLA.MODE=2)

Name: SYNCBUSY
Offset: 0x10
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
       GP1GP0 
Access R/WR/W 
Reset 00 
Bit 15141312111098 
 CLOCKSYNC   MASK0    
Access RR 
Reset 00 
Bit 76543210 
   ALARM0 CLOCKFREQCORRENABLESWRST 
Access RRRRR 
Reset 00000 

Bits 16, 17 – GPn General Purpose n

These bits are for user-defined general purpose use.

Bit 15 – CLOCKSYNC Clock Read Sync Enable Synchronization Busy Status

ValueDescription
0 Write synchronization for CTRLA.CLOCKSYNC bit is complete.
1 Write synchronization for CTRLA.CLOCKSYNC bit is ongoing.

Bit 11 – MASK0 Mask 0 Synchronization Busy Status

ValueDescription
0 Write synchronization for MASK0 register is complete.
1 Write synchronization for MASK0 register is ongoing.

Bit 5 – ALARM0 Alarm 0 Synchronization Busy Status

ValueDescription
0 Write synchronization for ALARM0 register is complete.
1 Write synchronization for ALARM0 register is ongoing.

Bit 3 – CLOCK Clock Register Synchronization Busy Status

ValueDescription
0 Read/write synchronization for CLOCK register is complete.
1 Read/write synchronization for CLOCK register is ongoing.

Bit 2 – FREQCORR Frequency Correction Synchronization Busy Status

ValueDescription
0 Write synchronization for FREQCORR register is complete.
1 Write synchronization for FREQCORR register is ongoing.

Bit 1 – ENABLE Enable Synchronization Busy Status

ValueDescription
0 Write synchronization for CTRLA.ENABLE bit is complete.
1 Write synchronization for CTRLA.ENABLE bit is ongoing.

Bit 0 – SWRST Software Reset Synchronization Busy Status

ValueDescription
0 Write synchronization for CTRLA.SWRST bit is complete.
1 Write synchronization for CTRLA.SWRST bit is ongoing.