36 Instruction Set Summary

ARITHMETIC AND LOGIC INSTRUCTIONS
MnemonicsOperandsDescriptionOperationFlags#Clocks
ADDRd, RrAdd two Registers without CarryRd ← Rd + RrZ,C,N,V,H1
ADCRd, RrAdd two Registers with CarryRd ← Rd + Rr + CZ,C,N,V,H1
ADIWRdl,KAdd Immediate to WordRdh:Rdl ← Rdh:Rdl + KZ,C,N,V,S2
SUBRd, RrSubtract two RegistersRd ← Rd - RrZ,C,N,V,H1
SUBIRd, KSubtract Constant from Register Rd ← Rd - KZ,C,N,V,H1
SBCRd, RrSubtract two Registers with CarryRd ← Rd - Rr - CZ,C,N,V,H1
SBCIRd, KSubtract Constant from Reg with Carry.Rd ← Rd - K - CZ,C,N,V,H1
SBIWRdl,KSubtract Immediate from WordRdh:Rdl ← Rdh:Rdl - KZ,C,N,V,S2
ANDRd, RrLogical AND RegistersRd ← Rd · RrZ,N,V1
ANDIRd, KLogical AND Register and ConstantRd ← Rd · KZ,N,V1
ORRd, RrLogical OR RegistersRd ← Rd v RrZ,N,V1
ORIRd, KLogical OR Register and ConstantRd ← Rd v KZ,N,V1
EORRd, RrExclusive OR RegistersRd ← Rd ⊕ RrZ,N,V1
COMRdOne’s ComplementRd ← 0xFF - RdZ,C,N,V1
NEGRdTwo’s ComplementRd ← 0x00 - RdZ,C,N,V,H1
SBRRd,KSet Bit(s) in RegisterRd ← Rd v KZ,N,V1
CBRRd,KClear Bit(s) in RegisterRd ← Rd · (0xFF - K)Z,N,V1
INCRdIncrementRd ← Rd + 1Z,N,V1
DECRdDecrementRd ← Rd - 1 Z,N,V1
TSTRdTest for Zero or MinusRd ← Rd · Rd Z,N,V1
CLRRdClear RegisterRd ← Rd ⊕ RdZ,N,V1
SERRdSet RegisterRd ← 0xFFNone1
MULRd, RrMultiply UnsignedR1:R0 ← Rd x RrZ,C2
MULSRd, RrMultiply SignedR1:R0 ← Rd x RrZ,C2
MULSURd, RrMultiply Signed with UnsignedR1:R0 ← Rd x RrZ,C2
FMULRd, RrFractional Multiply UnsignedR1:R0 ← (Rd x Rr) << 1Z,C2
FMULSRd, RrFractional Multiply SignedR1:R0 ← (Rd x Rr) << 1Z,C2
FMULSURd, RrFractional Multiply Signed with UnsignedR1:R0 ← (Rd x Rr) << 1Z,C2
BRANCH INSTRUCTIONS
MnemonicsOperandsDescriptionOperationFlags#Clocks
RJMPkRelative JumpPC ← PC + k + 1None2
IJMPIndirect Jump to (Z)PC ← Z None2
JMP(1)kDirect JumpPC ← kNone3
RCALLkRelative Subroutine Call PC ← PC + k + 1None3
ICALLIndirect Call to (Z)PC ← ZNone3
CALL(1)kDirect Subroutine Call PC ← kNone4
RETSubroutine ReturnPC ← STACKNone4
RETIInterrupt ReturnPC ← STACKI4
CPSERd,RrCompare, Skip if Equalif (Rd = Rr) PC ← PC + 2 or 3None1/2/3
CPRd,RrCompareRd - RrZ, N,V,C,H1
CPCRd,RrCompare with CarryRd - Rr - CZ, N,V,C,H1
CPIRd,KCompare Register with ImmediateRd - KZ, N,V,C,H1
SBRCRr, bSkip if Bit in Register Clearedif (Rr(b)=0) PC ← PC + 2 or 3 None1/2/3
SBRSRr, bSkip if Bit in Register is Setif (Rr(b)=1) PC ← PC + 2 or 3None1/2/3
SBICA, bSkip if Bit in I/O Register Clearedif (I/O(A,b)=1) PC ← PC + 2 or 3 None1/2/3
SBISA, bSkip if Bit in I/O Register is Setif (I/O(A,b)=1) PC ← PC + 2 or 3None1/2/3
BRBSs, kBranch if Status Flag Setif (SREG(s) = 1) then PC←PC+k + 1None1/2
BRBCs, kBranch if Status Flag Clearedif (SREG(s) = 0) then PC←PC+k + 1None1/2
BREQ kBranch if Equal if (Z = 1) then PC ← PC + k + 1None1/2
BRNE kBranch if Not Equalif (Z = 0) then PC ← PC + k + 1None1/2
BRCS kBranch if Carry Setif (C = 1) then PC ← PC + k + 1None1/2
BRCC kBranch if Carry Clearedif (C = 0) then PC ← PC + k + 1None1/2
BRSH kBranch if Same or Higher if (C = 0) then PC ← PC + k + 1None1/2
BRLO kBranch if Lowerif (C = 1) then PC ← PC + k + 1None1/2
BRMI kBranch if Minusif (N = 1) then PC ← PC + k + 1None1/2
BRPL kBranch if Plus if (N = 0) then PC ← PC + k + 1None1/2
BRGE kBranch if Greater or Equal, Signedif (N ⊕ V= 0) then PC ← PC + k + 1None1/2
BRLT kBranch if Less Than Zero, Signedif (N ⊕ V= 1) then PC ← PC + k + 1None1/2
BRHS kBranch if Half Carry Flag Setif (H = 1) then PC ← PC + k + 1None1/2
BRHC kBranch if Half Carry Flag Clearedif (H = 0) then PC ← PC + k + 1None1/2
BRTS kBranch if T Flag Setif (T = 1) then PC ← PC + k + 1None1/2
BRTC kBranch if T Flag Clearedif (T = 0) then PC ← PC + k + 1None1/2
BRVS kBranch if Overflow Flag is Setif (V = 1) then PC ← PC + k + 1None1/2
BRVC kBranch if Overflow Flag is Clearedif (V = 0) then PC ← PC + k + 1None1/2
BRIE kBranch if Interrupt Enabledif ( I = 1) then PC ← PC + k + 1None1/2
BRID kBranch if Interrupt Disabledif ( I = 0) then PC ← PC + k + 1None1/2
BIT AND BIT-TEST INSTRUCTIONS
MnemonicsOperandsDescriptionOperationFlags#Clocks
SBIP,bSet Bit in I/O RegisterI/O(P,b) ← 1None2
CBIP,bClear Bit in I/O RegisterI/O(P,b) ← 0None2
LSLRdLogical Shift LeftRd(n+1) ← Rd(n), Rd(0) ← 0Z,C,N,V1
LSRRdLogical Shift RightRd(n) ← Rd(n+1), Rd(7) ← 0Z,C,N,V1
ROLRdRotate Left Through CarryRd(0)←C,Rd(n+1)← Rd(n),C¬Rd(7)Z,C,N,V1
RORRdRotate Right Through CarryRd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)Z,C,N,V1
ASRRdArithmetic Shift RightRd(n) ← Rd(n+1), n=0...6Z,C,N,V1
SWAPRdSwap NibblesRd(3...0)←Rd(7...4),Rd(7...4)¬Rd(3...0)None1
BSETsFlag SetSREG(s) ← 1SREG(s)1
BCLRsFlag ClearSREG(s) ← 0 SREG(s)1
BSTRr, bBit Store from Register to TT ← Rr(b)T1
BLDRd, bBit load from T to RegisterRd(b) ← TNone1
SECSet CarryC ← 1C1
CLCClear CarryC ← 0 C1
SENSet Negative FlagN ← 1N1
CLNClear Negative FlagN ← 0 N1
SEZSet Zero FlagZ ← 1Z1
CLZClear Zero FlagZ ← 0 Z1
SEIGlobal Interrupt EnableI ← 1I1
CLIGlobal Interrupt DisableI ← 0 I1
SESSet Signed Test FlagS ← 1S1
CLSClear Signed Test FlagS ← 0 S1
SEVSet Two’s Complement Overflow.V ← 1V1
CLVClear Two’s Complement OverflowV ← 0 V1
SETSet T in SREGT ← 1T1
CLTClear T in SREGT ← 0 T1
SEHSet Half Carry Flag in SREGH ← 1H1
CLHClear Half Carry Flag in SREGH ← 0 H1
DATA TRANSFER INSTRUCTIONS
MnemonicsOperandsDescriptionOperationFlags#Clocks
MOVRd, RrMove Between RegistersRd ← RrNone1
MOVWRd, RrCopy Register WordRd+1:Rd ← Rr+1:RrNone1
LDIRd, KLoad ImmediateRd ← KNone1
LDRd, XLoad IndirectRd ← (X)None2
LDRd, X+Load Indirect and Post-IncrementRd ← (X), X ← X + 1None2
LDRd, - XLoad Indirect and Pre-DecrementX ← X - 1, Rd ← (X)None2
LDRd, YLoad IndirectRd ← (Y)None2
LDRd, Y+Load Indirect and Post-IncrementRd ← (Y), Y ← Y + 1None2
LDRd, - YLoad Indirect and Pre-DecrementY ← Y - 1, Rd ← (Y)None2
LDDRd,Y+qLoad Indirect with DisplacementRd ← (Y + q)None2
LDRd, ZLoad Indirect Rd ← (Z)None2
LDRd, Z+Load Indirect and Post-IncrementRd ← (Z), Z ← Z+1None2
LDRd, -ZLoad Indirect and Pre-DecrementZ ← Z - 1, Rd ← (Z)None2
LDDRd, Z+qLoad Indirect with DisplacementRd ← (Z + q)None2
LDSRd, kLoad Direct from SRAMRd ← (k)None2
STX, RrStore Indirect(X) ← RrNone2
STX+, RrStore Indirect and Post-Increment(X) ← Rr, X ← X + 1None2
ST- X, RrStore Indirect and Pre-DecrementX ← X - 1, (X) ← RrNone2
STY, RrStore Indirect(Y) ← RrNone2
STY+, RrStore Indirect and Post-Increment(Y) ← Rr, Y ← Y + 1None2
ST- Y, RrStore Indirect and Pre-DecrementY ← Y - 1, (Y) ← RrNone2
STDY+q,RrStore Indirect with Displacement(Y + q) ← RrNone2
STZ, RrStore Indirect(Z) ← RrNone2
STZ+, RrStore Indirect and Post-Increment(Z) ← Rr, Z ← Z + 1None2
ST-Z, RrStore Indirect and Pre-DecrementZ ← Z - 1, (Z) ← RrNone2
STDZ+q,RrStore Indirect with Displacement(Z + q) ← RrNone2
STSk, RrStore Direct to SRAM(k) ← RrNone2
LPMLoad Program MemoryR0 ← (Z)None3
LPMRd, ZLoad Program MemoryRd ← (Z)None3
LPMRd, Z+Load Program Memory and Post-IncRd ← (Z), Z ← Z+1None3
SPMStore Program Memory(Z) ← R1:R0None-
INRd, AIn from I/O LocationRd ← I/O (A)None1
OUTA, RrOut to I/O LocationI/O (A) ← RrNone1
PUSHRrPush Register on StackSTACK ← RrNone2
POPRdPop Register from StackRd ← STACKNone2
MCU CONTROL INSTRUCTIONS
MnemonicsOperandsDescriptionOperationFlags#Clocks
NOPNo OperationNo OperationNone1
SLEEPSleep(see specific descr. for Sleep function)None1
WDRWatchdog Reset(see specific descr. for WDR/timer)None1
BREAKBreakFor On-chip Debug OnlyNoneN/A