4.2.2 High-Speed Analog Comparator with Slope Compensation

The comparator output is high whenever the peak tank current reaches a reference current value. This reference value is represented by a voltage connected to the comparator.

The dsPIC33A features a highly versatile, high-speed analog comparator, which includes an integrated slope-compensated Digital-to-Analog Converter (DAC). This configuration provides flexibility and precision for cycle-by-cycle operation.

In this application, the DAC is set to slope compensation mode with a negative slope. Slope compensation is used to achieve a sharper intersection between the current feedback signal and the DAC reference value, enhancing the accuracy of the capture event.

The output of the comparator serves as the Capture - PCI source for the primary PWM. Slope generation is synchronized with the PG1H signal: the slope starts at the rising edge of PWM1H and stops when the comparator output is triggered.

In push-pull output mode, triggers are generated once for both the positive and negative half-cycles. To address this issue, the ADC trigger available in PG1 is utilized. This trigger can be configured with a 1:N ratio, allowing it to activate once every N cycles.

    //1:2 adc trigger 
    PG1EVT1bits.ADTR1PS = 1; 

This trigger is then routed to an internal PG event C, which is subsequently mapped to an internal PPS pin. The PPS pin is used to initiate the Slope Start event.

The comparator output is routed through the internal PPS to serve as the Slope Stop signal.

DAC3SLPCONbits.SLPSTRT = 14;    // EVTC through RPV15
DAC3SLPCONbits.SLPSTOPB = 13;   // CMP3out through RPV14
DAC3DATbits.DACDAT = 1000;		// Initial value for start-up
DAC3SLPDAT = 900;				// Slope data for start-up
DAC3CONbits.UPDTRG = 0b10;      // After any write to DACDATxDACDAT[15:0],
								// DACDATxDACLOW[15:0] or SLPDATxSLPDAT[15:0], 
							    // a start condition sets the UPDATE bit
DAC3SLPCONbits.SLOPEN = 1;		// Enable slope mode