4.2.1 Primary PWM

The primary side of the LLC converter is configured in a half-bridge arrangement and is controlled by PWM Generator 1 (PG1). PG1 operates in Resonant Mode, with its output set to a push-pull configuration. This setup introduces additional complexity in managing triggers for the DAC and secondary PWM, which will be discussed in subsequent sections.

Both external and internal comparator signals can be utilized to generate capture events. These events are registered by PG1 through the PWM Control Input (PCI) block. In this implementation, the PWM Control Input – Current Limit (PCI-CL) block is used.

The PCI blocks facilitate the configuration of conditions under which a pulse is recognized as an event, including various acceptance qualifiers and other parameters. This document presents the specific features and settings employed in the implementation; for comprehensive details, please refer to the device datasheet.

The relevant configuration settings are as follows:

PG1CLPCI2 = 1<<30;    			// Comparator 3 output selected as PCI source signal
PG1CLPCI1bits.TSYNCDIS = 1;     // Termination of Latched PCI occurs immediately
PG1CLPCI1bits.TERM = 1;         // Auto terminate: PCI source transitions to inactive 
PG1CLPCI1bits.TERMPS = 0;       // PCI Termination Polarity Select bit : non inverted
PG1CLPCI1bits.PPS = 0;          // PCI Polarity Selection : PCI source is not inverted
PG1CLPCI1bits.PSYNC = 0;        // PCI Sync Control: PCI source not synchronized to PWM EOC
PG1CLPCI1bits.AQPS = 1;         // Acceptance Qualifier Polarity: LEB active inverted
								// accepts PCI signal when LEB duration is over
PG1CLPCI1bits.AQSS = 2;         // Acceptance Qualifier Source: LEB is active

PG1LEBbits.LEB = 20 << 4;       // Leading Edge Blanking Duration: ~1us
PG1LEBbits.PHR = 0b1;           // Rising edge of PWMx will trigger LEB counter
PG1LEBbits.TRGB = 1;            // PGxTRIGB event triggers LEB, rising edge masks near EOC
PG1IOCON1bits.CAPSRC = 0b11;    // Capture time base at assertion of PCI Current Limit

The acceptance qualifier for the PCI source is the inverted Leading Edge Blanking (LEB) counter. This configuration ensures that capture pulses are ignored while the LEB counter is active, thereby enabling robust minimum frequency clamping.

The same LEB counter is also utilized to blank pulses occurring at the very edge of a transition; specifically, if the difference between the period register (PGPER) and the capture register (PG1CAP) is less than a defined threshold D, where D corresponds to period bits representing approximately a 20 kHz difference (D = 120 equates to 24 kHz). Additionally, capture pulses are disregarded during the negative cycle, or when the PG1L signal is high. The combined implementation of both high- and low-frequency clamping is illustrated below.