1.2 Block Diagram
(Ask a Question)The following figure shows the various blocks available in IGLOO 2 FPGA.
The following table lists the features supported by devices in the IGLOO 2 FPGA family.
Peripherals | Features 1, 2 | M2GL005 (S) | M2GL010 (S/T/TS) | M2GL025 (T/TS) | M2GL050 (T/TS) | M2GL060 (T/TS) | M2GL090 (T/TS) | M2GL150 (T/TS) |
---|---|---|---|---|---|---|---|---|
Logic/DSP | Maximum Logic Elements (4LUT + DFF)3 | 6,060 | 12,084 | 27,696 | 56,340 | 56,520 | 86,184 | 146,124 |
Math Blocks (18 × 18) | 11 | 22 | 34 | 72 | 72 | 84 | 240 | |
PLLs and CCCs | 2 | 2 | 6 | 6 | 6 | 6 | 8 | |
SPI/HPDMA/PDMA | 1 each | 1 each | 1 each | 1 each | 1 each | 1 each | 1 each | |
Fabric Interface Controllers | 1 | 1 | 1 | 2 | 1 | 1 | 2 | |
Data Security | AES256, SHA256, and RNG | AES256, SHA256, and RNG | AES256, SHA256, and RNG | AES256, SHA256, and RNG | AES256, SHA256, RNG, ECC, and PUF | AES256, SHA256, RNG, ECC, and PUF | AES256, SHA256, RNG, ECC, and PUF | |
Memory | eNVM (KB) | 128 | 256 | 256 | 256 | 256 | 512 | 512 |
LSRAM18K Blocks | 10 | 21 | 31 | 69 | 69 | 109 | 236 | |
μSRAM 1K Blocks | 11 | 22 | 34 | 72 | 72 | 112 | 240 | |
eSRAM (KB) | 64 | 64 | 64 | 64 | 64 | 64 | 64 | |
Total RAM (Kbit) | 703 | 912 | 1104 | 1826 | 1826 | 2586 | 5000 | |
High Speed | DDR Controllers | 1 × 18 | 1 × 18 | 1 × 18 | 2 × 36 | 1 × 18 | 1 × 18 | 2 × 36 |
SerDes Lanes (T) | 0 | 4 | 4 | 8 | 4 | 4 | 16 | |
PCIe End Points | 0 | 1 | 1 | 2 | 2 | 2 | 4 | |
User I/Os | MSIO (3.3V) | 119 | 123 | 157 | 139 | 279 | 309 | 292 |
MSIOD (2.5V) | 28 | 40 | 40 | 62 | 40 | 40 | 106 | |
DDRIO (2.5V) | 66 | 70 | 70 | 176 | 76 | 76 | 176 | |
Total User I/O | 209 | 233 | 267 | 377 | 395 | 425 | 574 | |
Grades | Commercial(C), Industrial (I), Military (M), and Automotive (T1/T2) | C,I, T1, and T2 | C,I, M, T1, and T2 | C,I, M, T1, and T2 | C,I, M,T1, and T2 | C,I, M, T1, and T2 | C,I, M, T1, andT2 | C,I, and M |
Note:
- Feature availability is package dependent.
- Data security features are only available in S and TS devices.
- Total logic might vary based on utilization of DSP and memories in your design. See UG0445: IGLOO2 FPGA and SmartFusion2 SoC FPGA Fabric User Guide for more information about DSP and memories.