1.3 I/Os Per Package

The following table provides the packaging options for IGLOO 2 devices.

Table 1-2. Packaging Options
Package Options1Pitch (mm)Length × Width (mm)
FCSG32520.511 × 11
VF(G)2562,30.814 × 14
FCSG53620.516 × 16
VF(G)4002, 30.817 × 17
FCV(G)4842, 30.819 × 19
TQ(G)1442, 40.520 × 20
FG(G)4842, 51.023 × 23
VFG7840.823 × 23
FG(G)6762, 31.027 × 27
FG(G)89621.031 × 31
FC(G)115221.035 × 35
Note:
  1. All the mentioned packages are available with lead and lead free. Package VFG784 is available only in lead-free.
  2. (G) indicates that the package is RoHS 6/6 Compliant/Pb-free.
  3. Automotive T2 grade devices are available in the VF(G)256, VF(G)400, FG(G)484, and FG(G)676 packages.
  4. The TQ(G)144 package is available in T2 grade by the end of February 2017.
  5. Automotive T1grade devices are available in the FG(G)484 package.

The following table provides the I/O details for IGLOO 2 devices.

Table 1-3. I/Os per Package
DevicesM2GL005 (S)M2GL010 (T/TS)1,2M2GL025 (T/TS)1M2GL050 (T/TS)1M2GL060 (T/TS)1M2GL090 (T/TS)1,3,4M2GL150 (T/TS)5
FCSG325I/Os——180200200180—
Lanes——2224—
VFG256I/Os161138138————
Lanes—22————
FCSG536I/Os——————293
Lanes——————4
VFG400I/Os171195207207207——
Lanes—4444——
FCV(G)484I/Os——————248
Lanes——————4
TQ(G)144I/Os8484—————
Lanes———————
FG(G)484I/Os209233267267267267—
Lanes—44444—
FG(G)676I/Os————387425—
Lanes————44—
VFG784I/Os————395——
Lanes————4——
FG(G)896I/Os———377———
Lanes———8———
FC(G)1152I/Os——————574
Lanes——————16
Note:
  1. Mil Temperature 010/025/050/060/090 devices are only available in the FG(G)484 package.
  2. M2GL010(S) device is only available in TQ(G)144 package. M2GL010 (T/TS) devices are not available in TQ(G)144 package.
  3. 090FCS(G)325 is 11x13.5 pkg dimension.
  4. The M2GL090 (T/TS) device in the FCSG325 package is available with an ordering code of XZ48. The XZ48 ordering code pre-configures the device for Auto Update mode. Minimum Order quantities apply, contact your local Microchip sales office for details.
  5. Mil Temperature 150 devices are only available in the FC(G)1152 package.
    • Highlighted cells indicate that the device packages have vertical migration capability.

The following table lists the features per device and its package combination.

Table 1-4. Features per Device/Package Combination
PackageDevicesMDDR FDDRCrystal Oscillators 5G SerDes Lanes1PCIe EndpointsMSIO (3.3V max.) 2MSIOD (2.5 max.)3DDRIO (2.5V max.)Total User I/Os
TQ(G)1444M2GL005 (S)——1——5292384
M2GL010 (S)——1——50112384
VFG2564M2GL005 (S)——1——1191230161
M2GL010 (T/TS)×185—1 21 66864138
M2GL025 (T/TS)×185—1 21 66864138
FCSG3254M2GL025 (T/TS)×185—1 21 942264180
M2GL050 (T/TS)×185—1 21 902288200
M2GL060 (T/TS)×185—1 42 1142264200
M2GL090 (T/TS)×185—1 42 1041264180
VFG4004M2GL005(S) ×185—1——792864171
M2GL010 (T/TS)×185—1 41 993264195
M2GL025 (T/TS)×185—1 41 1113264207
M2GL050 (T/TS)×185—1 41 873288207
M2GL060 (T/TS)×185—1 42 1113264207
FCV(G)4844M2GL150 (T/TS) ×185×1851 4479134123248
FG(G)484 4M2GL005 (S)×185—1——1152866209
M2GL010 (T/TS)×185—1411234070233
M2GL025 (T/TS)×185—1411574070267
M2GL050 (T/TS)×186—14110540122267
M2GL060 (T/TS)×185—1421574070267
M2GL090 (T/TS)×185—1421574070267
FC(G)536 4M2GL150 (T/TS)×185×185144715116126293
FG(G)676 4M2GL060 (T/TS)×185—1422714076387
M2GL090 (T/TS)×185—1423094076425
VFG784M2GL060 (T/TS)×185—1422794076395
FG(G)896 4,8M2GL050 (T/TS)×369×36918213962176377
FC(G)11524M2GL150 (T/TS) ×3610×36101164292106176574
Note:
  1. Maximum SerDes rate for military temperature devices is 3.125 bps.
  2. Number of differential MSIO is number of MSIOs/2 for even and number of MSIOs and 1/2 for odd.
  3. Number of differential MSIOD is number of MSIODs/2 for even and number of MSIODs and 1/2 for odd.
  4. All the packages mentioned above are available with lead and lead free. (G) indicates that the package is RoHS 6/6 Compliant/Pb-free.
  5. DDR supports ×18, ×16, ×9, and ×8 modes
  6. DDR supports ×18 and ×16 modes
  7. 4 PCIe Gen1/Gen2 endpoints ×1 lane configuration.
  8. DDR3 is non-compliant. Call technical support for details.
  9. DDR supports ×36, ×32, ×18, and ×16 modes.
  10. DDR supports ×36, ×32, ×18, ×16, ×9, and ×8 modes.
    • SerDes is not available in Automotive T1 grade.

The following table lists the programming interfaces that are available in IGLOO 2 FPGA.

Table 1-5. Programming Interfaces
PackageDevicesJTAGSPI_0Flash_GOLDEN_NSystem Controller SPI Port
TQ(G)1441M2GL005 (S)YesYesNoNo
M2GL010 (S)YesYesNoNo
VFG2561M2GL005 (S)YesYesYesYes
M2GL010 (T/TS)YesYesYesNo
M2GL025 (T/TS)YesYesYesNo
FCSG3251M2GL025 (T/TS)YesYesNoNo
M2GL050 (T/TS)YesYesNoNo
M2GL060 (T/TS)YesYesNoNo
M2GL090 (T/TS)YesYesNoNo
VFG4001M2GL005 (S)YesYesYesYes
M2GL010 (T/TS)YesYesYesYes
M2GL025 (T/TS)YesYesYesYes
M2GL050 (T/TS)YesYesYesYes
M2GL060 (T/TS)YesYesYesYes
FCV(G)4841M2GL150 (T/TS)YesYesYesYes
FG(G)4841M2GL005 (S)YesYesYesYes
M2GL010 (T/TS)YesYesYesYes
M2GL025(T/TS)YesYesYesYes
M2GL050 (T/TS)YesYesYesYes
M2GL060 (T/TS)YesYesYesYes
M2GL090(T/TS)YesYesYesYes
FCSG5361M2GL150 (T/TS)YesYesYesYes
FG(G)6761M2GL060(T/TS)YesYesYesYes
M2GL090(T/TS)YesYesYesYes
VFG784M2GL060 (T/TS)YesYesYesYes
FG(G)8961M2GL050 (T/TS)YesYesYesYes
FC(G)11521M2GL150 (T/TS)YesYesYesYes
Note:
  1. All the mentioned packages are available with lead and lead free. (G) indicates that the package is RoHS 6/6 Compliant/Pb-free.

The following table lists the chip resources needed for programming modes.

Table 1-6. Chip Resources Needed for Programming Modes
Programming ModeJTAGSPI_0Flash_GOLDEN_NSystem Controller SPI Port
External FlashPro4/5YesNoNoNo
External uP–TAG ClientYesNoNoNo
External uP–SPI ClientNoNoNoYes
Auto ProgrammingNoYesYesNo
2-Step IAPNoYesNoNo
Programming RecoveryNoYesNoNo