The following considerations must be
taken care of while implementing the application
The RC filter used in this
application is the simplest component to generate analog signal from PWM output.
For analog signal output with lesser ripples, noise components, etc., better
signal conditioning must be performed.
The output of the RC Filter will
be an analog signal with reduced amplitude. Based on the need, a suitable
amplifier circuit can be added to solve the purpose.
The PWM frequency can be
increased further by reducing the resolution of the sine-wave. However, reduced
resolution results in increased step size of the waveform, which would result in
ripples and non-smooth waveform.
The design parameters should be
configured such that TimerTop / (TimerFreq / CPUFreq)
shall be greater than 21 cycles for application in assembly language and greater
that 46 cycles for application in C language. Breaching this may result in sine
wave generated with undesired frequency. For different configurations, refer
Table 2-2.
Frequency of the output sine wave
depends on the CPU frequency and Timer1 Clock frequency. The clock used from
Timer1 is a PLL with internal RC oscillator as reference. Hence, it is necessary
to calibrate the RC oscillator to generate the desired frequency of sine
wave.
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