9.4 SRAM Data Memory

Data memory locations include the I/O memory, the internal SRAM memory, the Non-Volatile Memory (NVM) Lock bits, and the Flash memory. The following figure shows how the ATtiny102/ATtiny104 SRAM Memory is organized.

The first 64 locations are reserved for I/O memory, while the following 32 data memory locations address the internal data SRAM.

The Non-Volatile Memory (NVM) Lock bits and all the Flash memory sections are mapped to the data memory space. These locations appear as read-only for device firmware.

The four different addressing modes for data memory are direct, indirect, indirect with pre-decrement, and indirect with post-increment. In the register file, registers R26 to R31 function as pointer registers for indirect addressing.

The IN and OUT instructions can access all 64 locations of I/O memory. Direct addressing using the LDS and STS instructions reaches the 128 locations between 0x0040 and 0x00BF.

The indirect addressing reaches the entire data memory space. When using indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented.