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ATtiny102/ATtiny104 Complete 8-bit AVR Microcontroller
Introduction
Feature
1 Description
2 Configuration Summary
3 Ordering Information
4 Block Diagram
5 Pin Configurations
5.1 Pin Descriptions
6 I/O Multiplexing
7 General Information
7.1 Resources
7.2 Data Retention
7.3 About Code Examples
8 AVR CPU Core
8.1 Overview
8.2 Features
8.3 Block Diagram
8.4 ALU – Arithmetic Logic Unit
8.5 Status Register
8.6 General Purpose Register File
8.7 The X-register, Y-register, and Z-register
8.8 Stack Pointer
8.9 Accessing 16-bit Registers
8.10 Instruction Execution Timing
8.11 Reset and Interrupt Handling
8.12 Register Description
9 AVR Memories
9.1 Overview
9.2 Features
9.3 In-System Reprogrammable Flash Program Memory
9.4 SRAM Data Memory
9.5 I/O Memory
10 Clock System
10.1 Overview
10.2 Clock Distribution
10.3 Clock Subsystems
10.4 Clock Sources
10.5 System Clock Prescaler
10.6 Starting
10.7 Register Description
11 Power Management and Sleep Modes
11.1 Overview
11.2 Features
11.3 Sleep Modes
11.4 Power Reduction Register
11.5 Minimizing Power Consumption
11.6 Register Description
12 SCRST - System Control and Reset
12.1 Overview
12.2 Features
12.3 Resetting the AVR
12.4 Reset Sources
12.5 Watchdog Timer
12.6 Register Description
13 Interrupts
13.1 Overview
13.2 Interrupt Vectors
13.3 External Interrupts
13.4 Register Description
14 I/O-Ports
14.1 Overview
14.2 Features
14.3 I/O Pin Equivalent Schematic
14.4 Ports as General Digital I/O
14.5 Register Description
15 USART - Universal Synchronous Asynchronous Receiver Transceiver
15.1 Overview
15.2 Features
15.3 Block Diagram
15.4 Clock Generation
15.5 Frame Formats
15.6 USART Initialization
15.7 Data Transmission – The USART Transmitter
15.8 Data Reception – The USART Receiver
15.9 Asynchronous Data Reception
15.10 Multi-Processor Communication Mode
15.11 Examples of Baud Rate Setting
15.12 Register Description
16 USARTSPI - USART in SPI Mode
16.1 Overview
16.2 Features
16.3 Clock Generation
16.4 SPI Data Modes and Timing
16.5 Frame Formats
16.6 Data Transfer
16.7 AVR USART MSPIM vs. AVR SPI
16.8 Register Description
17 TC0 - 16-bit Timer/Counter0 with PWM
17.1 Overview
17.2 Features
17.3 Block Diagram
17.4 Definitions
17.5 Registers
17.6 Accessing 16-bit Timer/Counter Registers
17.7 Timer/Counter Clock Sources
17.8 Counter Unit
17.9 Input Capture Unit
17.10 Output Compare Units
17.11 Compare Match Output Unit
17.12 Modes of Operation
17.13 Timer/Counter Timing Diagrams
17.14 Register Description
18 AC - Analog Comparator
18.1 Overview
18.2 Features
18.3 Block Diagram
18.4 Register Description
19 ADC - Analog to Digital Converter
19.1 Overview
19.2 Features
19.3 Block Diagram
19.4 Operation
19.5 Starting a Conversion
19.6 Prescaling and Conversion Timing
19.7 Changing Channel or Reference Selection
19.8 ADC Input Channels
19.9 ADC Voltage Reference
19.10 ADC Noise Canceler
19.11 Analog Input Circuitry
19.12 Analog Noise Canceling Techniques
19.13 ADC Accuracy Definitions
19.14 ADC Conversion Result
19.15 Register Description
20 MEMPROG- Memory Programming
20.1 Overview
20.2 Features
20.3 Non-Volatile Memories (NVM)
20.4 Accessing the NVM
20.5 Self programming
20.6 External Programming
20.7 Register Description
21 TPI-Tiny Programming Interface
21.1 Overview
21.2 Features
21.3 Block Diagram
21.4 Physical Layer of Tiny Programming Interface
21.5 Instruction Set
21.6 Accessing the Non-Volatile Memory Controller
21.7 Control and Status Space Register Descriptions
22 Electrical Characteristics
22.1 Absolute Maximum Ratings*
22.2 DC Characteristics
22.3 Speed
22.4 Clock Characteristics
22.5 System and Reset Characteristics
22.6 Analog Comparator Characteristics
22.7 ADC Characteristics
22.8 Serial Programming Characteristics
23 Typical Characteristics
23.1 Active Supply Current
23.2 Idle Supply Current
23.3 Supply Current of I/O Modules
23.4 Power-down Supply Current
23.5 Pin Driver Strength
23.6 Pin Threshold and Hysteresis
23.7 Analog Comparator Offset
23.8 Pin Pull-up
23.9 Internal Oscillator Speed
23.10 VLM Thresholds
23.11 Current Consumption of Peripheral Units
23.12 Current Consumption in Reset and Reset Pulsewidth
24 Register Summary
24.1 Note
25 Instruction Set Summary
26 Packaging Information
26.1 8-pin UDFN
26.2 8-pin SOIC150
26.3 14-pin SOIC150
27 Errata
27.1 ATtiny102
27.2 ATtiny104
28 Datasheet Revision History
28.1 Rev D - 10/2016
28.2 Rev C - 07/2016
28.3 Rev B - 06/2016
28.4 Rev A - 02/2016
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