6 I/O Multiplexing

Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the PORT I/O pins.

Table 6-1. PORT Function Multiplexing
14-pin8-pinPin nameSpecialINT(3)ADC(3)ACUSARTTimerProgramming(8)
11(1)VCC
22PA[0](2)CLKIPCINT0ADC0AIN0T0TPICLK
33PA[1](5)PCINT1ADC1AIN1OC0BTPIDATA
44PA[2]RESETPCINT2RESET
5-PA[3](9)PCINT3OC0A
6-PA[4](9)PCINT4ICP0
7-PA[5](5)(9)PCINT5ADC2OC0B
8-PA[6]PCINT6ADC3
9-PA[7]PCINT7
10-PB[0]PCINT8ADC4
115PB[1](6)CLKOPCINT9/INT0ADC5XCK0OC0A
126PB[2](7)PCINT10ADC6TxD0ICP0
137PB[3](4)(9)PCINT11ADC7ACORxD0T0
148GND
Note:
  1. On the 8-pin UDFN package, the thermal pad should not be connected as well.
  2. Priority of CLKI is higher than ADC0. When EXT_CLK is enabled, ADC channel will not work and DIDR0 will not disable the digital input buffer.
  3. When both PCINT and the corresponding ADC channel are enabled, the digital input buffer will not be disabled.
  4. When ACO is enabled, ADC, TC and USART RX inputs are not disabled.
  5. When OC0B is enabled, ADC and AC will continue to receive inputs on that channel if enabled.
  6. When CLKO is enable in PB[1], OCA will get lower priority.
  7. When USART is enabled, the users must ensure that ADC channel corresponding to the TxD0 pin is not used. Because DIDR0 register will only control the input buffer, not the output part.
  8. During reset/external programming, all pins are treated as inputs and outputs are disabled.
  9. Alternative location when enabling T/C Remap