6.2 144-lead Package Pinout

Table 6-1. 144-lead Package Pinout
LQFP Pin LFBGA/TFBGA Ball UFBGA Ball Power Rail I/O Type Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C PIO Peripheral D Reset State
Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST
102 C11 E11 VDDIO GPIO_AD PA0 I/O WKUP0(1) I PWMC0_ PWMH0 O TIOA0 I/O A17 O I2SC0_M CK O PIO, I, PU, ST
99 D12 F11 VDDIO GPIO_AD PA1 I/O WKUP1(1) I PWMC0_ PWML0 O TIOB0 I/O A18 O I2SC0_C K I/O PIO, I, PU, ST
93 E12 G12 VDDIO GPIO PA2 I/O WKUP2(1) I PWMC0_ PWMH1 O DATRG I PIO, I, PU, ST
91 F12 G11 VDDIO GPIO_AD PA3 I/O PIODC0(2) I TWD0 I/O LONCOL 1 I PCK2 O PIO, I, PU, ST
77 K12 L12 VDDIO GPIO PA4 I/O WKUP3/P IODC1(3) I TWCK0 O TCLK0 I UTXD1 O PIO, I, PU, ST
73 M11 N13 VDDIO GPIO_AD PA5 I/O WKUP4/P IODC2(3) I PWMC1_ PWML3 O ISI_D4 I URXD1 I PIO, I, PU, ST
114 B9 B11 VDDIO GPIO_AD PA6 I/O PCK0 O UTXD1 O PIO, I, PU, ST
35 L2 N1 VDDIO CLOCK PA7 I/O XIN32(4) I PWMC0_ PWMH3 O PIO, HiZ
36 M2 N2 VDDIO CLOCK PA8 I/O XOUT32(4) O PWMC1_ PWMH3 O AFE0_ADTRG I PIO, HiZ
75 M12 L11 VDDIO GPIO_AD PA9 I/O WKUP6/P IODC3(3) I URXD0 I ISI_D3 I PWMC0_ PWMFI0 I PIO, I, PU, ST
66 L9 M10 VDDIO GPIO_AD PA10 I/O PIODC4(2) I UTXD0 O PWMC0_ PWMEXTRG0 I RD I PIO, I, PU, ST
64 J9 N10 VDDIO GPIO_AD PA11 I/O WKUP7/P IODC5(3) I QCS O PWMC0_ PWMH0 O PWMC1_ PWML0 O PIO, I, PU, ST
68 L10 N11 VDDIO GPIO_AD PA12 I/O PIODC6(2) I QIO1 I/O PWMC0_ PWMH1 O PWMC1_ PWMH0 O PIO, I, PU, ST
42 M3 M4 VDDIO GPIO_AD PA13 I/O PIODC7(2) I QIO0 I/O PWMC0_ PWMH2 O PWMC1_ PWML1 O PIO, I, PU, ST
51 K6 M6 VDDIO GPIO_CL K PA14 I/O WKUP8/P IODCEN1(3) I QSCK O PWMC0_ PWMH3 O PWMC1_ PWMH1 O PIO, I, PU, ST
49 L5 N6 VDDIO GPIO_AD PA15 I/O D14 I/O TIOA1 I/O PWMC0_ PWML3 O I2SC0_W S I/O PIO, I, PU, ST
45 K5 L4 VDDIO GPIO_AD PA16 I/O D15 I/O TIOB1 I/O PWMC0_ PWML2 O I2SC0_DI I PIO, I, PU, ST
25 J1 J4 VDDIO GPIO_AD PA17 I/O AFE0_AD6(5) I QIO2 I/O PCK1 O PWMC0_ PWMH3 O PIO, I, PU, ST
24 H2 J3 VDDIO GPIO_AD PA18 I/O AFE0_AD7(5) I PWMC1_ PWMEXTRG1 I PCK2 O A14 O PIO, I, PU, ST
23 H1 J2 VDDIO GPIO_AD PA19 I/O AFE0_AD8/WKUP9(6) I PWMC0_ PWML0 O A15 O I2SC1_M CK O PIO, I, PU, ST
22 H3 J1 VDDIO GPIO_AD PA20 I/O AFE0_AD9/WKUP10(6) I PWMC0_ PWML1 O A16 O I2SC1_C K I/O PIO, I, PU, ST
32 K2 M1 VDDIO GPIO_AD PA21 I/O AFE0_AD1/ PIODCEN 2(8) I RXD1 I PCK1 O PWMC1_ PWMFI0 I PIO, I, PU, ST
37 K3 M2 VDDIO GPIO_AD PA22 I/O PIODCCL K(2) I RK I/O PWMC0_ PWMEXTRG1 I NCS2 O PIO, I, PU, ST
46 L4 N5 VDDIO GPIO_AD PA23 I/O SCK1 I/O PWMC0_ PWMH0 O A19 O PWMC1_ PWML2 O PIO, I, PU, ST
56 L7 N8 VDDIO GPIO_AD PA24 I/O RTS1 O PWMC0_ PWMH1 O A20 O ISI_PCK I PIO, I, PU, ST
59 K8 L8 VDDIO GPIO_AD PA25 I/O CTS1 I PWMC0_ PWMH2 O A23 O MCCK O PIO, I, PU, ST
62 J8 M9 VDDIO GPIO PA26 I/O DCD1 I TIOA2 O MCDA2 I/O PWMC1_ PWMFI1 I PIO, I, PU, ST
70 J10 N12 VDDIO GPIO_AD PA27 I/O DTR1 O TIOB2 I/O MCDA3 I/O ISI_D7 I PIO, I, PU, ST
112 C9 C11 VDDIO GPIO PA28 I/O DSR1 I TCLK1 I MCCDA I/O PWMC1_ PWMFI2 I PIO, I, PU, ST
129 A6 A7 VDDIO GPIO PA29 I/O RI1 I TCLK2 I PIO, I, PU, ST
116 A10 A11 VDDIO GPIO PA30 I/O WKUP11(1) I PWMC0_ PWML2 O PWMC1_ PWMEXTRG0 I MCDA0 I/O I2SC0_D O O PIO, I, PU, ST
118 C8 C10 VDDIO GPIO_AD PA31 I/O SPI0_NP CS1 I/O PCK2 O MCDA1 I/O PWMC1_ PWMH2 O PIO, I, PU, ST
21 H4 H2 VDDIO GPIO PB0 I/O AFE0_AD10/ RTCOUT 0(7) I PWMC0_ PWMH0 O RXD0 I TF I/O PIO, I, PU, ST
20 G3 H1 VDDIO GPIO PB1 I/O AFE1_AD0/ RTCOUT 1(7) I PWMC0_ PWMH1 O GTSUCO MP O TXD0 I/O TK I/O PIO, I, PU, ST
26 J2 K1 VDDIO GPIO PB2 I/O AFE0_AD5(5) I CANTX0 O CTS0 I SPI0_NP CS0 I/O PIO, I, PU, ST
31 J3 L1 VDDIO GPIO_AD PB3 I/O AFE0_AD2/WKUP12(6) I CANRX0 I PCK2 O RTS0 O ISI_D2 I PIO, I, PU, ST
105 A12 C13 VDDIO GPIO_ML B PB4 I/O TDI(9) I TWD1 I/O PWMC0_ PWMH2 O

MLBCLK

I

TXD1 I/O PIO, I, PU, ST
109 C10 C12 VDDIO GPIO_ML B PB5 I/O TDO/TRA CESWO/ WKUP13(9) O TWCK1 O PWMC0_ PWML0 O

MLBDAT

I/O

TD O O, PU
79 J11 K11 VDDIO GPIO PB6 I/O SWDIO/T MS(9) I PIO,I,ST
89 F9 H13 VDDIO GPIO PB7 I/O SWCLK/TCK(9) I PIO,I,ST
141 A3 B2 VDDIO CLOCK PB8 I/O XOUT(10) O PIO, HiZ
142 A2 A2 VDDIO CLOCK PB9 I/O XIN(10) I PIO, HiZ
87 G12 J10 VDDIO GPIO PB12 I/O ERASE(9) I PWMC0_ PWML1 O GTSUCO MP O PCK0 O PIO, I, PD, ST
144 B2 A1 VDDIO GPIO_AD PB13 I/O DAC0(11) O PWMC0_ PWML2 O PCK0 O SCK0 I/O PIO, I, PU, ST
11 E4 F2 VDDIO GPIO_AD PC0 I/O AFE1_AD9(5) I D0 I/O PWMC0_ PWML0 O PIO, I, PU, ST
38 J4 M3 VDDIO GPIO_AD PC1 I/O D1 I/O PWMC0_ PWML1 O PIO, I, PU, ST
39 K4 N3 VDDIO GPIO_AD PC2 I/O D2 I/O PWMC0_ PWML2 O PIO, I, PU, ST
40 L3 N4 VDDIO GPIO_AD PC3 I/O D3 I/O PWMC0_ PWML3 O PIO, I, PU, ST
41 J5 L3 VDDIO GPIO_AD PC4 I/O D4 I/O PIO, I, PU, ST
58 L8 M8 VDDIO GPIO_AD PC5 I/O D5 I/O TIOA6 I/O PIO, I, PU, ST
54 K7 L7 VDDIO GPIO_AD PC6 I/O D6 I/O TIOB6 I/O PIO, I, PU, ST
48 M4 L5 VDDIO GPIO_AD PC7 I/O D7 I/O TCLK6 I PIO, I, PU, ST
82 J12 K13 VDDIO GPIO_AD PC8 I/O NWR0/N WE O TIOA7 I/O PIO, I, PU, ST
86 G11 J11 VDDIO GPIO_AD PC9 I/O NANDOE O TIOB7 I/O PIO, I, PU, ST
90 F10 H12 VDDIO GPIO_AD PC10 I/O NANDWE O TCLK7 I PIO, I, PU, ST
94 F11 F13 VDDIO GPIO_AD PC11 I/O NRD O TIOA8 I/O PIO, I, PU, ST
17 F4 G2 VDDIO GPIO_AD PC12 I/O AFE1_AD3(5) I NCS3 O TIOB8 I/O CANRX1 I PIO, I, PU, ST
19 G2 H3 VDDIO GPIO_AD PC13 I/O AFE1_AD1(5) I NWAIT I PWMC0_ PWMH3 O O PIO, I, PU, ST
97 E10 F12 VDDIO GPIO_AD PC14 I/O NCS0 O TCLK8 I CANTX1 O PIO, I, PU, ST
18 G1 H4 VDDIO GPIO_AD PC15 I/O AFE1_AD2(5) I NCS1/SD CS O PWMC0_ PWML3 O PIO, I, PU, ST
100 D11 E12 VDDIO GPIO_AD PC16 I/O A21/NAN DALE O PIO, I, PU, ST
103 B12 E10 VDDIO GPIO_AD PC17 I/O A22/NAN DCLE O PIO, I, PU, ST
111 B10 B12 VDDIO GPIO_AD PC18 I/O A0/NBS0 O PWMC0_ PWML1 O PIO, I, PU, ST
117 D8 B10 VDDIO GPIO_AD PC19 I/O A1 O PWMC0_ PWMH2 O PIO, I, PU, ST
120 A9 C9 VDDIO GPIO_AD PC20 I/O A2 O PWMC0_ PWML2 O PIO, I, PU, ST
122 A7 A9 VDDIO GPIO_AD PC21 I/O A3 O PWMC0_ PWMH3 O PIO, I, PU, ST
124 C7 A8 VDDIO GPIO_AD PC22 I/O A4 O PWMC0_ PWML3 O PIO, I, PU, ST
127 C6 C7 VDDIO GPIO_AD PC23 I/O A5 O TIOA3 I/O PIO, I, PU, ST
130 B6 D7 VDDIO GPIO_AD PC24 I/O A6 O TIOB3 I/O SPI1_SP CK O PIO, I, PU, ST
133 C5 C6 VDDIO GPIO_AD PC25 I/O A7 O TCLK3 I SPI1_NP CS0 I/O PIO, I, PU, ST
13 F2 F4 VDDIO GPIO_AD PC26 I/O AFE1_AD7(5) I A8 O TIOA4 I/O SPI1_MIS O I PIO, I, PU, ST
12 E2 F3 VDDIO GPIO_AD PC27 I/O AFE1_AD8(5) I A9 O TIOB4 I/O SPI1_MO SI O PIO, I, PU, ST
76 L12 L13 VDDIO GPIO_AD PC28 I/O A10 O TCLK4 I SPI1_NP CS1 I/O PIO, I, PU, ST
16 F3 G1 VDDIO GPIO_AD PC29 I/O AFE1_AD4(5) I A11 O TIOA5 I/O SPI1_NP CS2 O PIO, I, PU, ST
15 F1 G3 VDDIO GPIO_AD PC30 I/O AFE1_AD5(5) I A12 O TIOB5 I/O SPI1_NP CS3 O PIO, I, PU, ST
14 E1 G4 VDDIO GPIO_AD PC31 I/O AFE1_AD6(5) I A13 O TCLK5 I PIO, I, PU, ST
1 D4 B1 VDDIO GPIO_AD PD0 I/O DAC1(11) I GTXCK I PWMC1_ PWML0 O SPI1_NP CS1 I/O DCD0 I PIO, I, PU, ST
132 B5 B6 VDDIO GPIO PD1 I/O GTXEN O PWMC1_ PWMH0 O SPI1_NP CS2 I/O DTR0 O PIO, I, PU, ST
131 A5 A6 VDDIO GPIO PD2 I/O GTX0 O PWMC1_ PWML1 O SPI1_NP CS3 I/O DSR0 I PIO, I, PU, ST
128 B7 B7 VDDIO GPIO PD3 I/O GTX1 O PWMC1_ PWMH1 O UTXD4 O RI0 I PIO, I, PU, ST
126 D6 C8 VDDIO GPIO_CL K PD4 I/O GRXDV I PWMC1_ PWML2 O TRACED 0 O DCD2 I PIO, I, PU, ST
125 D7 B8 VDDIO GPIO_CL K PD5 I/O GRX0 I PWMC1_ PWMH2 O TRACED 1 O DTR2 O PIO, I, PU, ST
121 A8 B9 VDDIO GPIO_CL K PD6 I/O GRX1 I PWMC1_ PWML3 O TRACED 2 O DSR2 I PIO, I, PU, ST
119 B8 A10 VDDIO GPIO_CL K PD7 I/O GRXER I PWMC1_ PWMH3 O TRACED 3 O RI2 I PIO, I, PU, ST
113 E9 A12 VDDIO GPIO_CL K PD8 I/O GMDC O PWMC0_ PWMFI1 I TRACEC LK O PIO, I, PU, ST
110 D9 A13 VDDIO GPIO_CL K PD9 I/O GMDIO I/O PWMC0_ PWMFI2 I AFE1_AD TRG I PIO, I, PU, ST
101 C12 D13 VDDIO GPIO_ML B PD10 I/O GCRS I PWMC0_ PWML0 O TD O

MLBSIG

I/O

PIO, I, PD, ST
98 E11 E13 VDDIO GPIO_AD PD11 I/O GRX2 I PWMC0_ PWMH0 O GTSUCO MP O ISI_D5 I PIO, I, PU, ST
92 G10 G13 VDDIO GPIO_AD PD12 I/O GRX3 I CANTX1 O SPI0_NP CS2 O ISI_D6 I PIO, I, PU, ST
88 G9 H11 VDDIO GPIO_CL K PD13 I/O GCOL I O PIO, I, PU, ST
84 H10 J12 VDDIO GPIO_AD PD14 I/O GRXCK I O PIO, I, PU, ST
106 A11 D11 VDDIO GPIO_AD PD15 I/O GTX2 O RXD2 I NWR1/N BS1 O PIO, I, PU, ST
78 K11 K10 VDDIO GPIO_AD PD16 I/O GTX3 O TXD2 I/O O PIO, I, PU, ST
74 L11 M13 VDDIO GPIO_AD PD17 I/O GTXER O SCK2 I/O O PIO, I, PU, ST
69 M10 M11 VDDIO GPIO_AD PD18 I/O NCS1/SD CS O RTS2 O URXD4 I PIO, I, PU, ST
67 M9 L10 VDDIO GPIO_AD PD19 I/O NCS3 O CTS2 I UTXD4 O PIO, I, PU, ST
65 K9 K9 VDDIO GPIO PD20 I/O PWMC0_ PWMH0 O SPI0_MIS O I/O GTSUCO MP O PIO, I, PU, ST
63 H9 L9 VDDIO GPIO_AD PD21 I/O PWMC0_ PWMH1 O SPI0_MO SI I/O TIOA11 I/O ISI_D1 I PIO, I, PU, ST
60 M8 N9 VDDIO GPIO_AD PD22 I/O PWMC0_ PWMH2 O SPI0_SP CK O TIOB11 I/O ISI_D0 I PIO, I, PU, ST
57 M7 N7 VDDIO GPIO_CL K PD23 I/O PWMC0_ PWMH3 O O PIO, I, PU, ST
55 M6 K7 VDDIO GPIO_AD PD24 I/O PWMC0_ PWML0 O RF I/O TCLK11 I ISI_HSYN C I PIO, I, PU, ST
52 M5 L6 VDDIO GPIO_AD PD25 I/O PWMC0_ PWML1 O SPI0_NP CS1 I/O URXD2 I ISI_VSYN C I PIO, I, PU, ST
53 L6 M7 VDDIO GPIO PD26 I/O PWMC0_ PWML2 O TD O UTXD2 O UTXD1 O PIO, I, PU, ST
47 J6 M5 VDDIO GPIO_AD PD27 I/O PWMC0_ PWML3 O SPI0_NP CS3 O TWD2 O ISI_D8 I PIO, I, PU, ST
71 K10 M12 VDDIO GPIO_AD PD28 I/O WKUP5(1) I URXD3 I - I TWCK2 O ISI_D9 I PIO, I, PU, ST
108 D10 B13 VDDIO GPIO_AD PD29 I/O O PIO, I, PU, ST
34 M1 L2 VDDIO GPIO_AD PD30 I/O AFE0_AD 0(5) I UTXD3 O ISI_D10 I PIO, I, PU, ST
2 D3 C3 VDDIO GPIO_AD PD31 I/O QIO3 I/O UTXD3 O PCK2 O ISI_D11 I PIO, I, PU, ST
4 C2 C2 VDDIO GPIO_AD PE0 I/O AFE1_AD 11(5) I D8 I/O TIOA9 I/O I2SC1_W S I/O PIO, I, PU, ST
6 A1 D2 VDDIO GPIO_AD PE1 I/O D9 I/O TIOB9 I/O I2SC1_D O O PIO, I, PU, ST
7 B1 D1 VDDIO GPIO_AD PE2 I/O D10 I/O TCLK9 I I2SC1_DI I PIO, I, PU, ST
10 E3 F1 VDDIO GPIO_AD PE3 I/O AFE1_AD 10(5) I D11 I/O TIOA10 I/O PIO, I, PU, ST
27 K1 K2 VDDIO GPIO_AD PE4 I/O AFE0_AD 4(5) I D12 I/O TIOB10 I/O PIO, I, PU, ST
28 L1 K3 VDDIO GPIO_AD PE5 I/O AFE0_AD 3(5) I D13 I/O TCLK10 I/O PIO, I, PU, ST
3 C3 E4 VDDOUT Power VDDOUT
5 C1 C1 VDDIN Power VDDIN
8 D2 E2 GND Reference VREFN I
9 D1 E1 VDDIO Reference VREFP I
83 H12 K12 VDDIO RST NRST I/O I, PU
85 H11 J13 VDDIO TEST TST I I, PD
30,43,72,80,96 G8,H6,H7 D6,F10,K6 VDDIO Power VDDIO
104 B11 D12 VDDIO TEST JTAGSEL I I, PD
29,33,50,81,107 E8,H5,H8 D5, G10, K5 VDDCOR E Power VDDCOR E
123 J7 D8 VDDPLL Power VDDPLL
134 E7 B4 VDDUTMI I Power VDDUTMI I
136 B4 A5 VDDUTMI I USBHS HSDM I/O
137 A4 A4 VDDUTMI I USBHS HSDP I/O
44,61,95,115,135,138 F5, F6, G4, G5, G6, G7 C5, D3, D10, H10, K4, K8 GND Ground GND
-- D5 E3 GNDANA Ground GNDANA
- E5 B5 GNDUTM I Ground GNDUTM I
- E6 B3 GNDPLL USB Ground GNDPLL USB
- F7 D9 GNDPLL Ground GNDPLL
139 B3 C4 VDDUTMI C Power VDDUTMI C
140 C4 A3 VBG VBG I
143 F8 D4 VDDPLL USB Power VDDPLL USB
Note:
  1. WKUPx can be used if the PIO Controller defines the I/O line as “input”.
  2. To select this extra function, refer to the 32.5.14 Parallel Capture Mode section in the Parallel Input/Output Controller (PIO) chapter.
  3. PIODCEN1/PIODCx has priority over WKUPx. Refer to the 32.5.14 Parallel Capture Mode section in the PIO chapter.
  4. Refer to the 23.4.2 Slow Clock Generator section in the Supply Controller (SUPC) chapter.
  5. To select this extra function, refer to the 33.5.2.1 I/O Lines section in the External Bus Interface (EBI) chapter. This selection is independent of the PIO line configuration. PIO lines must be configured according to required settings (PU or PD).
  6. Analog input has priority over WKUPx pin. To select the analog input, refer to the 33.5.2.1 I/O Lines section in the EBI chapter. WKUPx can be used if the PIO controller defines the I/O line as “input”.
  7. Analog input has priority over RTCOUTx pin. To select the analog input, refer to the 33.5.2.1 I/O Lines section in the EBI chapter. Refer to the 27.5.8 Waveform Generation section in the Real-Time Clock (RTC) chapter to select RTCOUTx.
  8. Analog input has priority over WKUPx pin. To select the analog input, refer to the 33.5.2.1 I/O Lines section in the EBI chapter. To select PIODCEN2, refer to the 32.5.14 Parallel Capture Mode in the PIO chapter.
  9. Refer to the System I/O Configuration Register (CCFG_SYSIO19.4.7 System I/O and CAN1 Configuration Register) in the Bus Matrix (MATRIX) chapter.
  10. Refer to the 30.5.3 Main Crystal Oscillator section in the Clock Generator chapter. This selection is independent of the PIO line configuration. PIO lines must be configured according to XINxx (I) and XOUTxx (O).
  11. DAC0 is selected when DACC_CHER.CH0 is set. DAC1 is selected when DACC_CHER.CH1 is set. Refer to the DACC Channel Enable Register in the Digital-to-Analog Converter Controller (DACC) chapter.