6.2 144-lead Package Pinout

Table 6-1. 144-lead Package Pinout
LQFP PinLFBGA/TFBGA BallUFBGA BallPower RailI/O TypePrimary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C PIO Peripheral D Reset State
SignalDirSignalDirSignalDirSignalDirSignalDirSignalDirSignal, Dir, PU, PD, HiZ, ST
102C11E11VDDIOGPIO_ADPA0I/OWKUP0(1)IPWMC0_ PWMH0OTIOA0I/OA17OI2SC0_M CKOPIO, I, PU, ST
99D12F11VDDIOGPIO_ADPA1I/OWKUP1(1)IPWMC0_ PWML0OTIOB0I/OA18OI2SC0_C KI/OPIO, I, PU, ST
93E12G12VDDIOGPIOPA2I/OWKUP2(1)IPWMC0_ PWMH1ODATRGIPIO, I, PU, ST
91F12G11VDDIOGPIO_ADPA3I/OPIODC0(2)ITWD0I/OLONCOL 1IPCK2OPIO, I, PU, ST
77K12L12VDDIOGPIOPA4I/OWKUP3/P IODC1(3)ITWCK0OTCLK0IUTXD1OPIO, I, PU, ST
73M11N13VDDIOGPIO_ADPA5I/OWKUP4/P IODC2(3)IPWMC1_ PWML3OISI_D4IURXD1IPIO, I, PU, ST
114B9B11VDDIOGPIO_ADPA6I/OPCK0OUTXD1OPIO, I, PU, ST
35L2N1VDDIOCLOCKPA7I/OXIN32(4)IPWMC0_ PWMH3OPIO, HiZ
36M2N2VDDIOCLOCKPA8I/OXOUT32(4)OPWMC1_ PWMH3OAFE0_ADTRGIPIO, HiZ
75M12L11VDDIOGPIO_ADPA9I/OWKUP6/P IODC3(3)IURXD0IISI_D3IPWMC0_ PWMFI0IPIO, I, PU, ST
66L9M10VDDIOGPIO_ADPA10I/OPIODC4(2)IUTXD0OPWMC0_ PWMEXTRG0IRDIPIO, I, PU, ST
64J9N10VDDIOGPIO_ADPA11I/OWKUP7/P IODC5(3)IQCSOPWMC0_ PWMH0OPWMC1_ PWML0OPIO, I, PU, ST
68L10N11VDDIOGPIO_ADPA12I/OPIODC6(2)IQIO1I/OPWMC0_ PWMH1OPWMC1_ PWMH0OPIO, I, PU, ST
42M3M4VDDIOGPIO_ADPA13I/OPIODC7(2)IQIO0I/OPWMC0_ PWMH2OPWMC1_ PWML1OPIO, I, PU, ST
51K6M6VDDIOGPIO_CL KPA14I/OWKUP8/P IODCEN1(3)IQSCKOPWMC0_ PWMH3OPWMC1_ PWMH1OPIO, I, PU, ST
49L5N6VDDIOGPIO_ADPA15I/OD14I/OTIOA1I/OPWMC0_ PWML3OI2SC0_W SI/OPIO, I, PU, ST
45K5L4VDDIOGPIO_ADPA16I/OD15I/OTIOB1I/OPWMC0_ PWML2OI2SC0_DIIPIO, I, PU, ST
25J1J4VDDIOGPIO_ADPA17I/OAFE0_AD6(5)IQIO2I/OPCK1OPWMC0_ PWMH3OPIO, I, PU, ST
24H2J3VDDIOGPIO_ADPA18I/OAFE0_AD7(5)IPWMC1_ PWMEXTRG1IPCK2OA14OPIO, I, PU, ST
23H1J2VDDIOGPIO_ADPA19I/OAFE0_AD8/WKUP9(6)IPWMC0_ PWML0OA15OI2SC1_M CKOPIO, I, PU, ST
22H3J1VDDIOGPIO_ADPA20I/OAFE0_AD9/WKUP10(6)IPWMC0_ PWML1OA16OI2SC1_C KI/OPIO, I, PU, ST
32K2M1VDDIOGPIO_ADPA21I/OAFE0_AD1/ PIODCEN 2(8)IRXD1IPCK1OPWMC1_ PWMFI0IPIO, I, PU, ST
37K3M2VDDIOGPIO_ADPA22I/OPIODCCL K(2)IRKI/OPWMC0_ PWMEXTRG1INCS2OPIO, I, PU, ST
46L4N5VDDIOGPIO_ADPA23I/OSCK1I/OPWMC0_ PWMH0OA19OPWMC1_ PWML2OPIO, I, PU, ST
56L7N8VDDIOGPIO_ADPA24I/ORTS1OPWMC0_ PWMH1OA20OISI_PCKIPIO, I, PU, ST
59K8L8VDDIOGPIO_ADPA25I/OCTS1IPWMC0_ PWMH2OA23OMCCKOPIO, I, PU, ST
62J8M9VDDIOGPIOPA26I/ODCD1ITIOA2OMCDA2I/OPWMC1_ PWMFI1IPIO, I, PU, ST
70J10N12VDDIOGPIO_ADPA27I/ODTR1OTIOB2I/OMCDA3I/OISI_D7IPIO, I, PU, ST
112C9C11VDDIOGPIOPA28I/ODSR1ITCLK1IMCCDAI/OPWMC1_ PWMFI2IPIO, I, PU, ST
129A6A7VDDIOGPIOPA29I/ORI1ITCLK2IPIO, I, PU, ST
116A10A11VDDIOGPIOPA30I/OWKUP11(1)IPWMC0_ PWML2OPWMC1_ PWMEXTRG0IMCDA0I/OI2SC0_D OOPIO, I, PU, ST
118C8C10VDDIOGPIO_ADPA31I/OSPI0_NP CS1I/OPCK2OMCDA1I/OPWMC1_ PWMH2OPIO, I, PU, ST
21H4H2VDDIOGPIOPB0I/OAFE0_AD10/ RTCOUT 0(7)IPWMC0_ PWMH0ORXD0ITFI/OPIO, I, PU, ST
20G3H1VDDIOGPIOPB1I/OAFE1_AD0/ RTCOUT 1(7)IPWMC0_ PWMH1OGTSUCO MPOTXD0I/OTKI/OPIO, I, PU, ST
26J2K1VDDIOGPIOPB2I/OAFE0_AD5(5)ICANTX0OCTS0ISPI0_NP CS0I/OPIO, I, PU, ST
31J3L1VDDIOGPIO_ADPB3I/OAFE0_AD2/WKUP12(6)ICANRX0IPCK2ORTS0OISI_D2IPIO, I, PU, ST
105A12 C13VDDIOGPIO_ML BPB4I/OTDI(9)ITWD1I/OPWMC0_ PWMH2O

MLBCLK

I

TXD1I/OPIO, I, PU, ST
109C10C12VDDIOGPIO_ML BPB5I/OTDO/TRA CESWO/ WKUP13(9)OTWCK1OPWMC0_ PWML0O

MLBDAT

I/O

TDOO, PU
79J11K11VDDIOGPIOPB6I/OSWDIO/T MS(9)IPIO,I,ST
89F9H13VDDIOGPIOPB7I/OSWCLK/TCK(9)IPIO,I,ST
141A3B2VDDIOCLOCKPB8I/OXOUT(10)OPIO, HiZ
142A2A2VDDIOCLOCKPB9I/OXIN(10)IPIO, HiZ
87G12J10VDDIOGPIOPB12I/OERASE(9)IPWMC0_ PWML1OGTSUCO MPOPCK0OPIO, I, PD, ST
144B2A1VDDIOGPIO_ADPB13I/ODAC0(11)OPWMC0_ PWML2OPCK0OSCK0I/OPIO, I, PU, ST
11E4F2VDDIOGPIO_ADPC0I/OAFE1_AD9(5)ID0I/OPWMC0_ PWML0OPIO, I, PU, ST
38J4M3VDDIOGPIO_ADPC1I/OD1I/OPWMC0_ PWML1OPIO, I, PU, ST
39K4N3VDDIOGPIO_ADPC2I/OD2I/OPWMC0_ PWML2OPIO, I, PU, ST
40L3N4VDDIOGPIO_ADPC3I/OD3I/OPWMC0_ PWML3OPIO, I, PU, ST
41J5L3VDDIOGPIO_ADPC4I/OD4I/OPIO, I, PU, ST
58L8M8VDDIOGPIO_ADPC5I/OD5I/OTIOA6I/OPIO, I, PU, ST
54K7L7VDDIOGPIO_ADPC6I/OD6I/OTIOB6I/OPIO, I, PU, ST
48M4L5VDDIOGPIO_ADPC7I/OD7I/OTCLK6IPIO, I, PU, ST
82J12K13VDDIOGPIO_ADPC8I/ONWR0/N WEOTIOA7I/OPIO, I, PU, ST
86G11J11VDDIOGPIO_ADPC9I/ONANDOEOTIOB7I/OPIO, I, PU, ST
90F10H12VDDIOGPIO_ADPC10I/ONANDWEOTCLK7IPIO, I, PU, ST
94F11F13VDDIOGPIO_ADPC11I/ONRDOTIOA8I/OPIO, I, PU, ST
17F4G2VDDIOGPIO_ADPC12I/OAFE1_AD3(5)INCS3OTIOB8I/OCANRX1IPIO, I, PU, ST
19G2H3VDDIOGPIO_ADPC13I/OAFE1_AD1(5)INWAITIPWMC0_ PWMH3OOPIO, I, PU, ST
97E10F12VDDIOGPIO_ADPC14I/ONCS0OTCLK8ICANTX1OPIO, I, PU, ST
18G1H4VDDIOGPIO_ADPC15I/OAFE1_AD2(5)INCS1/SD CSOPWMC0_ PWML3OPIO, I, PU, ST
100D11E12VDDIOGPIO_ADPC16I/OA21/NAN DALEOPIO, I, PU, ST
103B12E10VDDIOGPIO_ADPC17I/OA22/NAN DCLEOPIO, I, PU, ST
111B10B12VDDIOGPIO_ADPC18I/OA0/NBS0OPWMC0_ PWML1OPIO, I, PU, ST
117D8B10VDDIOGPIO_ADPC19I/OA1OPWMC0_ PWMH2OPIO, I, PU, ST
120A9C9VDDIOGPIO_ADPC20I/OA2OPWMC0_ PWML2OPIO, I, PU, ST
122A7A9VDDIOGPIO_ADPC21I/OA3OPWMC0_ PWMH3OPIO, I, PU, ST
124C7A8VDDIOGPIO_ADPC22I/OA4OPWMC0_ PWML3OPIO, I, PU, ST
127C6C7VDDIOGPIO_ADPC23I/OA5OTIOA3I/OPIO, I, PU, ST
130B6D7VDDIOGPIO_ADPC24I/OA6OTIOB3I/OSPI1_SP CKOPIO, I, PU, ST
133C5C6VDDIOGPIO_ADPC25I/OA7OTCLK3ISPI1_NP CS0I/OPIO, I, PU, ST
13F2F4VDDIOGPIO_ADPC26I/OAFE1_AD7(5)IA8OTIOA4I/OSPI1_MIS OIPIO, I, PU, ST
12E2F3VDDIOGPIO_ADPC27I/OAFE1_AD8(5)IA9OTIOB4I/OSPI1_MO SIOPIO, I, PU, ST
76L12L13VDDIOGPIO_ADPC28I/OA10OTCLK4ISPI1_NP CS1I/OPIO, I, PU, ST
16F3G1VDDIOGPIO_ADPC29I/OAFE1_AD4(5)IA11OTIOA5I/OSPI1_NP CS2OPIO, I, PU, ST
15F1G3VDDIOGPIO_ADPC30I/OAFE1_AD5(5)IA12OTIOB5I/OSPI1_NP CS3OPIO, I, PU, ST
14E1G4VDDIOGPIO_ADPC31I/OAFE1_AD6(5)IA13OTCLK5IPIO, I, PU, ST
1D4B1VDDIOGPIO_ADPD0I/ODAC1(11)IGTXCKIPWMC1_ PWML0OSPI1_NP CS1I/ODCD0IPIO, I, PU, ST
132B5B6VDDIOGPIOPD1I/OGTXENOPWMC1_ PWMH0OSPI1_NP CS2I/ODTR0OPIO, I, PU, ST
131A5A6VDDIOGPIOPD2I/OGTX0OPWMC1_ PWML1OSPI1_NP CS3I/ODSR0IPIO, I, PU, ST
128B7B7VDDIOGPIOPD3I/OGTX1OPWMC1_ PWMH1OUTXD4ORI0IPIO, I, PU, ST
126D6C8VDDIOGPIO_CL KPD4I/OGRXDVIPWMC1_ PWML2OTRACED 0ODCD2IPIO, I, PU, ST
125D7B8VDDIOGPIO_CL KPD5I/OGRX0IPWMC1_ PWMH2OTRACED 1ODTR2OPIO, I, PU, ST
121A8B9VDDIOGPIO_CL KPD6I/OGRX1IPWMC1_ PWML3OTRACED 2ODSR2IPIO, I, PU, ST
119B8A10VDDIOGPIO_CL KPD7I/OGRXERIPWMC1_ PWMH3OTRACED 3ORI2IPIO, I, PU, ST
113E9A12VDDIOGPIO_CL KPD8I/OGMDCOPWMC0_ PWMFI1ITRACEC LKOPIO, I, PU, ST
110D9A13VDDIOGPIO_CL KPD9I/OGMDIOI/OPWMC0_ PWMFI2IAFE1_AD TRGIPIO, I, PU, ST
101C12D13VDDIOGPIO_ML BPD10I/OGCRSIPWMC0_ PWML0OTDO

MLBSIG

I/O

PIO, I, PD, ST
98E11E13VDDIOGPIO_ADPD11I/OGRX2IPWMC0_ PWMH0OGTSUCO MPOISI_D5IPIO, I, PU, ST
92G10G13VDDIOGPIO_ADPD12I/OGRX3ICANTX1OSPI0_NP CS2OISI_D6IPIO, I, PU, ST
88G9H11VDDIOGPIO_CL KPD13I/OGCOLIOPIO, I, PU, ST
84H10J12VDDIOGPIO_ADPD14I/OGRXCKIOPIO, I, PU, ST
106A11D11VDDIOGPIO_ADPD15I/OGTX2ORXD2INWR1/N BS1OPIO, I, PU, ST
78K11K10VDDIOGPIO_ADPD16I/OGTX3OTXD2I/OOPIO, I, PU, ST
74L11M13VDDIOGPIO_ADPD17I/OGTXEROSCK2I/OOPIO, I, PU, ST
69M10M11VDDIOGPIO_ADPD18I/ONCS1/SD CSORTS2OURXD4IPIO, I, PU, ST
67M9L10VDDIOGPIO_ADPD19I/ONCS3OCTS2IUTXD4OPIO, I, PU, ST
65K9K9VDDIOGPIOPD20I/OPWMC0_ PWMH0OSPI0_MIS OI/OGTSUCO MPOPIO, I, PU, ST
63H9L9VDDIOGPIO_ADPD21I/OPWMC0_ PWMH1OSPI0_MO SII/OTIOA11I/OISI_D1IPIO, I, PU, ST
60M8N9VDDIOGPIO_ADPD22I/OPWMC0_ PWMH2OSPI0_SP CKOTIOB11I/OISI_D0IPIO, I, PU, ST
57M7N7VDDIOGPIO_CL KPD23I/OPWMC0_ PWMH3OOPIO, I, PU, ST
55M6K7VDDIOGPIO_ADPD24I/OPWMC0_ PWML0ORFI/OTCLK11IISI_HSYN CIPIO, I, PU, ST
52M5L6VDDIOGPIO_ADPD25I/OPWMC0_ PWML1OSPI0_NP CS1I/OURXD2IISI_VSYN CIPIO, I, PU, ST
53L6M7VDDIOGPIOPD26I/OPWMC0_ PWML2OTDOUTXD2OUTXD1OPIO, I, PU, ST
47J6M5VDDIOGPIO_ADPD27I/OPWMC0_ PWML3OSPI0_NP CS3OTWD2OISI_D8IPIO, I, PU, ST
71K10M12VDDIOGPIO_ADPD28I/OWKUP5(1)IURXD3I-ITWCK2OISI_D9IPIO, I, PU, ST
108D10B13VDDIOGPIO_ADPD29I/OOPIO, I, PU, ST
34M1L2VDDIOGPIO_ADPD30I/OAFE0_AD 0(5)IUTXD3OISI_D10IPIO, I, PU, ST
2D3C3VDDIOGPIO_ADPD31I/OQIO3I/OUTXD3OPCK2OISI_D11IPIO, I, PU, ST
4C2C2VDDIOGPIO_ADPE0I/OAFE1_AD 11(5)ID8I/OTIOA9I/OI2SC1_W SI/OPIO, I, PU, ST
6A1D2VDDIOGPIO_ADPE1I/OD9I/OTIOB9I/OI2SC1_D OOPIO, I, PU, ST
7B1D1VDDIOGPIO_ADPE2I/OD10I/OTCLK9II2SC1_DIIPIO, I, PU, ST
10E3F1VDDIOGPIO_ADPE3I/OAFE1_AD 10(5)ID11I/OTIOA10I/OPIO, I, PU, ST
27K1K2VDDIOGPIO_ADPE4I/OAFE0_AD 4(5)ID12I/OTIOB10I/OPIO, I, PU, ST
28L1K3VDDIOGPIO_ADPE5I/OAFE0_AD 3(5)ID13I/OTCLK10I/OPIO, I, PU, ST
3C3E4VDDOUTPowerVDDOUT
5C1C1VDDINPowerVDDIN
8D2E2GNDReferenceVREFNI
9D1E1VDDIOReferenceVREFPI
83H12K12VDDIORSTNRSTI/OI, PU
85H11J13VDDIOTESTTSTII, PD
30,43,72,80,96G8,H6,H7D6,F10,K6VDDIOPowerVDDIO
104B11D12VDDIOTESTJTAGSELII, PD
29,33,50,81,107E8,H5,H8D5, G10, K5VDDCOR EPowerVDDCOR E
123J7D8VDDPLLPowerVDDPLL
134E7B4VDDUTMI IPowerVDDUTMI I
136B4A5VDDUTMI IUSBHSHSDMI/O
137A4A4VDDUTMI IUSBHSHSDPI/O
44,61,95,115,135,138F5, F6, G4, G5, G6, G7C5, D3, D10, H10, K4, K8GNDGroundGND
--D5E3GNDANAGroundGNDANA
-E5B5GNDUTM IGroundGNDUTM I
-E6B3GNDPLL USBGroundGNDPLL USB
-F7D9GNDPLLGroundGNDPLL
139B3C4VDDUTMI CPowerVDDUTMI C
140C4A3VBGVBGI
143F8D4VDDPLL USBPowerVDDPLL USB
Note:
  1. WKUPx can be used if the PIO Controller defines the I/O line as “input”.
  2. To select this extra function, refer to the Parallel Capture Mode section in the Parallel Input/Output Controller (PIO) chapter.
  3. PIODCEN1/PIODCx has priority over WKUPx. Refer to the Parallel Capture Mode section in the PIO chapter.
  4. Refer to the Slow Clock Generator section in the Supply Controller (SUPC) chapter.
  5. To select this extra function, refer to the I/O Lines section in the External Bus Interface (EBI) chapter. This selection is independent of the PIO line configuration. PIO lines must be configured according to required settings (PU or PD).
  6. Analog input has priority over WKUPx pin. To select the analog input, refer to the I/O Lines section in the EBI chapter. WKUPx can be used if the PIO controller defines the I/O line as “input”.
  7. Analog input has priority over RTCOUTx pin. To select the analog input, refer to the I/O Lines section in the EBI chapter. Refer to the Waveform Generation section in the Real-Time Clock (RTC) chapter to select RTCOUTx.
  8. Analog input has priority over WKUPx pin. To select the analog input, refer to the I/O Lines section in the EBI chapter. To select PIODCEN2, refer to the Parallel Capture Mode in the PIO chapter.
  9. Refer to the System I/O Configuration Register (CCFG_SYSIO) in the Bus Matrix (MATRIX) chapter.
  10. Refer to the Main Crystal Oscillator section in the Clock Generator chapter. This selection is independent of the PIO line configuration. PIO lines must be configured according to XINxx (I) and XOUTxx (O).
  11. DAC0 is selected when DACC_CHER.CH0 is set. DAC1 is selected when DACC_CHER.CH1 is set. Refer to the DACC Channel Enable Register in the Digital-to-Analog Converter Controller (DACC) chapter.