41.6.4.3 SPI Mode Flow Diagram

Figure 41-6. SPI Mode Flow Diagram

The figure below shows Transmit Data Register Empty (TDRE), Receive Data Register Full (RDRF) and Transmission Register Empty (TXEMPTY) status flags behavior within the QSPI_SR during an 8-bit data transfer in Fixed mode, without DMA.

Figure 41-7. Status Register Flags Behavior