41.7.2 QSPI Mode Register


Bit	31	30	29	28	27	26	25	24
	DLYCS[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	DLYBCT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
					NBBITS[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
	TAMPCLR		CSMODE[1:0]			WDRBT	LLB	SMM
Access	R/W		R/W	R/W		R/W	R/W	R/W
Reset	0		0	0		0	0	0

Bits 31:24 – DLYCS[7:0] Minimum Inactive QCS Delay

This field defines the minimum delay between the deactivation and the activation of QCS. The DLYCS time guarantees the Client minimum deselect time.

If DLYCS written to ‘0’, one peripheral clock period is inserted by default.

Otherwise, the following equation determines the delay:

DLYCS = Minimum inactive × f_{peripheral clock}

Bits 23:16 – DLYBCT[7:0] Delay Between Consecutive Transfers

This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed.

When DLYBCT is written to ‘0’, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. In Serial Memory mode (SMM = 1), DLYBCT must be written to ‘0’ and no delay is inserted.

Otherwise, the following equation determines the delay:

DLYBCT = (Delay Between Consecutive Transfers × f_{peripheral clock}) / 32

Bits 11:8 – NBBITS[3:0] Number Of Bits Per Transfer

Value	Name	Description
0x0	8_BITS	8 bits transfer
0x1	9_BITS	9 bits transfer
0x2	10_BITS	10 bits transfer
0x3	11_BITS	11 bits transfer
0x4	12_BITS	12 bits transfer
0x5	13_BITS	13 bits transfer
0x6	14_BITS	14 bits transfer
0x7	15_BITS	15 bits transfer
0x8	16_BITS	16 bits transfer
0x9-0xF	-	Reserved

Bit 7 – TAMPCLR Tamper Clear Enable

Value	Description
0	A tamper detection event has no effect on QSPI scrambling keys.
1	A tamper detection event immediately clears QSPI scrambling keys.

Bits 5:4 – CSMODE[1:0] Chip Select Mode

The CSMODE field determines how the chip select is deasserted

Note: This field is forced to LASTXFER when SMM is written to ‘1’.

Value	Name	Description
0	NOT_RELOADED	The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer.
1	LASTXFER	The chip select is deasserted when the bit LASTXFER is written to ‘1’ and the character written in QSPI_TDR.TD has been transferred.
2	SYSTEMATICALLY	The chip select is deasserted systematically after each transfer.

Bit 2 – WDRBT Wait Data Read Before Transfer

0 (DISABLED): No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is.

1 (ENABLED): In SPI mode, a transfer can start only if the QSPI_RDR is empty, that is, does not contain any unread data. This mode prevents overrun error in reception.

The QSPI in SPI mode does not support the Wait Data Read Before Transfer feature, the WDRBT bit in the QSPI Mode Register (QSPI_MR) must be ignored.

Bit 1 – LLB Local Loopback Enable

0 (DISABLED): Local loopback path disabled.

1 (ENABLED): Local loopback path enabled.

LLB controls the local loopback on the data serializer for testing in SPI mode only. (MISO is internally connected on MOSI).

Bit 0 – SMM Serial Memory Mode

0 (SPI): The QSPI is in SPI mode.

1 (MEMORY): The QSPI is in Serial Memory mode.

Name:	QSPI_MR
Offset:	0x04
Reset:	0x00000000
Property:	Read/Write