54.5.2.2 ICM Region Configuration Structure Member

Register offset is calculated as ICM_DSCR+0x004+RID*(0x10).
Name: ICM_RCFG
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
  ALGO[2:0] PROCDLYSUIENECIEN 
Access R/WR/WR/WR/WR/WR/W 
Reset  
Bit 76543210 
 WCIENBEIENDMIENRHIEN EOMWRAPCDWBN 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset  

Bits 14:12 – ALGO[2:0] SHA Algorithm

Values which are not listed in the table must be considered as “reserved”.
ValueNameDescription
0 SHA1 SHA1 algorithm processed
1 SHA256 SHA256 algorithm processed

Bit 10 – PROCDLY Processing Delay

When SHA1 algorithm is processed, the runtime period is either 85 or 209 clock cycles.

When SHA256 algorithm is processed, the runtime period is either 72 or 194 clock cycles.

ValueNameDescription
0 SHORTEST SHA processing runtime is the shortest one.
1 LONGEST SHA processing runtime is the longest one.

Bit 9 – SUIEN Monitoring Status Updated Condition Interrupt (Default Enabled)

ValueNameDescription
0 The ICM_ISR.RSU[i] flag is set when the corresponding descriptor is loaded from memory to ICM.
1 The ICM_ISR.RSU[i] flag remains cleared even if the setting condition is met.

Bit 8 – ECIEN End Bit Condition Interrupt (Default Enabled)

ValueNameDescription
0 The ICM_ISR.REC[i] flag is set when the descriptor with the EOM bit set is processed.
1 The ICM_ISR.REC[i] flag remains cleared even if the setting condition is met.

Bit 7 – WCIEN Wrap Condition Interrupt Disable (Default Enabled)

ValueNameDescription
0 The ICM_ISR.RWC[i] flag is set when the WRAP bit is set in a descriptor of the main list.
1 ICM_ISR.RWC[i] flag remains cleared even if the setting condition is met.

Bit 6 – BEIEN Bus Error Interrupt Disable (Default Enabled)

ValueNameDescription
0 The flag is set when an error is reported on the system bus by the bus matrix.
1 The flag remains cleared even if the setting condition is met.

Bit 5 – DMIEN Digest Mismatch Interrupt Disable (Default Enabled)

ValueNameDescription
0 The ICM_ISR.RBE[i] flag is set when the hash value just calculated from the processed region differs from expected hash value.
1 The ICM_ISR.RBE[i] flag remains cleared even if the setting condition is met.

Bit 4 – RHIEN Region Hash Completed Interrupt Disable (Default Enabled)

ValueNameDescription
0 The ICM_ISR.RHC[i] flag is set when the field NEXT = 0 in a descriptor of the main or second list.
1 The ICM_ISR.RHC[i] flag remains cleared even if the setting condition is met.

Bit 2 – EOM End Of Monitoring

ValueNameDescription
0 The current descriptor does not terminate the monitoring.
1 The current descriptor terminates the Main List. WRAP value has no effect.

Bit 1 – WRAP Wrap Command

ValueNameDescription
0 The next region descriptor address loaded is the current region identifier descriptor address incremented by 0x10.
1 The next region descriptor address loaded is ICM_DSCR.

Bit 0 – CDWBN Compare Digest or Write Back Digest

ValueNameDescription
0 The digest is written to the Hash area.
1 The digest value is compared to the digest stored in the Hash area.