33.5.1 Hardware Interface
The following table details the connections to be applied between the EBI pins and the external devices for each Memory Controller.
|
Signals: |
Pins of the Interfaced Device | ||
|---|---|---|---|
| 8-bit Static Device | 2 x 8-bit Static Devices | 16-bit Static Device | |
| Controller | SMC | ||
| D0–D7 | D0–D7 | D0–D7 | D0–D7 |
| D8–D15 | – | D8–D15 | D8–D15 |
| A0/NBS0 | A0 | – | NLB |
| A1 | A1 | A0 | A0 |
| A2–A23 | A[2:23] | A[1:22] | A[1:22] |
| NCS0 | CS | CS | CS |
| NCS1 | CS | CS | CS |
| NCS2 | CS | CS | CS |
| NCS3/NANDCS | CS | CS | CS |
| NRD | OE | OE | OE |
| NWR0/NWE | WE | WE (see Note) | WE |
| NWR1/NBS1 | – | WE (see Note) | NUB |
Note: NWR1 enables upper byte writes. NWR0 enables lower byte
writes.
|
Signals: |
Power supply | Pins of the Interfaced Device |
|---|---|---|
| NAND Flash | ||
| Controller | NFC | |
| D0–D15 | VDDIO | D0–D15 |
| A0/NBS0 | VDDIO | – |
| A1 | VDDIO | – |
| A2–A10 | VDDIO | – |
| A11 | VDDIO | – |
| A12 | VDDIO | – |
| A13–A14 | VDDIO | – |
| A15 | VDDIO | – |
| A16 | VDDIO | – |
| A17 | VDDIO | – |
| A18 | VDDIO | – |
| A19 | VDDIO | – |
| A20 | VDDIO | – |
| A21/NANDALE | VDDIO | ALE |
| A22/NANDCLE | VDDIO | CLE |
| A23 | VDDIO | – |
| NCS0 | VDDIO | – |
| NCS1 | VDDIO | – |
| NCS2 | VDDIO | – |
| NCS3/NANDCS | VDDIO | CE |
| NANDOE | VDDIO | OE |
| NANDWE | VDDIO | WE |
| NRD | VDDIO | – |
| NWR0/NWE | VDDIO | – |
| NWR1/NBS1 | VDDIO | – |
| Pxx | VDDIO | CE |
| Pxx | VDDIO | RDY |