7.6.1 Backup Mode

The purpose of Backup mode is to achieve the lowest power consumption possible in a system which is performing periodic wakeups to perform tasks but not requiring fast startup time.

The Supply Controller, zero-power Power-On Reset (POR), RTT, RTC, backup SRAM, backup registers and 32 kHz oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The regulator and the core supply are off.

Backup mode is based on the Cortex-M7 Deep-Sleep mode with the voltage regulator disabled.

Wakeup from Backup mode is done through WKUP0–13 pins, the supply monitor (SM), the RTT, or an RTC wakeup event.

Backup mode is entered by using the VROFFbit in the Supply Controller Control Register (SUPC_CR) and the SLEEPDEEP bit in the Cortex-M7 System Control Register set to 1. Refer to information on Power Management in the" ARM Cortex-M7 documentation", which is available for download at www.arm.com.

To enter Backup mode, follow these steps:

  1. Set the SLEEPDEEP bit of the Cortex-M7 processor.
  2. Set the VROFF bit of SUPC_CR.

Exit from Backup mode occurs as a result of one of the following enabled wakeup events:

  • WKUP0–13 pins (level transition, configurable debouncing)
  • Supply Monitor alarm
  • RTC alarm
  • RTT alarm
Note: If PLLA is enabled with the Main Crystal Oscillator as the clock source for Main Clock (MAINCK), the following sequence must be followed before entering into backup mode:
  1. Switch Main Clock (MAINCK) to Slow Clock (SLCK) by using PMC_MCKR.CSS.
  2. Disable the PLLA by writing MUL = 0 or DIV = 0.
  3. Disable the Main Crystal Oscillator.
  4. Add Wait time in the range of milliseconds.
  5. Enter backup mode.